VHDL - Hierarchical block <FF> is unconnected in block <Demux>. It will be removed from the design - vhdl

Question

NOTE: D and filtered_right should be connected in the picture.
Hello guys, I am having a difficulty with creating a circuit as one on the picture. The idea is that there is a rotary knot and with every rotation to the right some counter would increment and every rotation to the left it will decrement. When reached some value, I want some LEDs to glow. The principle on which it works is as following: if the left signal activates first, than it is rotation to right, otherwise a rotation to left. But when filtered, the logic is as it is in the code. If there is a rising edge (if the Q and D differ on the D Flip Flop), and the D is a '1', but meanwhile the other signal is '1' then it is a rotation to right, otherwise, a rotaton to left.
I am using a Spartan 3AN-Starter Kit FPGA. I described the filter and DFF in two separate entities and used them as components in my main project, but the warnings continually signal that they remain unconnected no matter what I do, even though it successfully synthesize. I would like to know why is that.
Here is a drawing of the circuit, my VHDL code and the warnings:
This is the main project:
--Main project
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use WORK.all;
entity Demux is
port ( led : OUT std_logic_vector(7 downto 0);
turn_right, turn_left,clk: IN std_logic);
subtype smallint is integer range 0 to 80;
end Demux;
architecture Behavioral of Demux is
component dff
port (set,reset,D,clk: IN std_logic;
Q: OUT std_logic);
end component;
component filter
port (clk,turn_right,turn_left: in std_logic;
filtered_right, filtered_left: out std_logic);
end component;
signal counter: smallint:=0;
signal Q: std_logic;
signal filtered_right: std_logic :='0';
signal filtered_left: std_logic := '0';
signal set: std_logic;
signal reset: std_logic;
begin
set <= '0';
reset <='0';
FF: dff port map (
set=>set,
reset=>reset,
D=>filtered_right,
clk=>clk,
Q=>Q);
filt: filter port map (
turn_right=>turn_right,
turn_left=>turn_left,
filtered_right=>filtered_right,
filtered_left=>filtered_left,
clk=>clk);
compare: process (clk,Q) is
begin
if ((clk'event) and (clk='1')) then
if ((filtered_right /= Q) and (filtered_right='1')) then
if (filtered_left = '1') then
counter <= counter + 1;
elsif (filtered_left = '0') then
counter <= counter - 1;
end if;
end if;
if (counter>80) or (counter<0) then
counter <=0;
end if;
end if;
end process compare;
led(0) <= '1' when counter = 10;
led(1) <= '1' when counter = 20;
led(2) <= '1' when counter = 30;
led(3) <= '1' when counter = 40;
led(4) <= '1' when counter = 50;
led(5) <= '1' when counter = 60;
led(6) <= '1' when counter = 70;
led(7) <= '1' when counter = 80;
end Behavioral;
Here is my realization of the DFF:
Library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
Entity dff is
port (D,set,reset,clk: in std_logic;
Q: out std_logic);
end dff;
Architecture behavioral of dff is
begin
dff: process (clk,set,reset,D) is
begin
if ((clk'event) and (clk='1')) then
if (reset='1') then
Q<='0';
elsif (set='1') then
Q<='1';
else
Q<=D;
end if;
end if;
end process dff;
end behavioral;
Here is my realization of the filter:
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity filter is
port (clk,turn_right,turn_left: in std_logic;
filtered_right, filtered_left: out std_logic);
end filter;
architecture Behavioral of filter is
begin
filter: process(clk, turn_right,turn_left) is
variable rotary_conc: std_logic_vector(1 downto 0);
variable filtered_left_temp, filtered_right_temp: std_logic;
begin
if ((clk'event) and (clk='1')) then
rotary_conc:=turn_left & turn_right;
case rotary_conc is
when "00" => filtered_right_temp := '0';
filtered_left_temp := filtered_left_temp;
when "01" => filtered_right_temp := filtered_right_temp;
filtered_left_temp := '0';
when "10" => filtered_right_temp := filtered_right_temp;
filtered_left_temp :='1';
when "11" => filtered_right_temp := '1';
filtered_left_temp := filtered_left_temp;
when OTHERS => filtered_right_temp := filtered_right_temp;
filtered_left_temp := filtered_left_temp;
end case;
filtered_right<=filtered_right_temp;
filtered_left<=filtered_left_temp;
end if;
end process filter;
end Behavioral;
Just so you know, the filter exists because there is a chatter because of the mechanic nature of the rotary knot. That chatter can produce false incrementation/decrementation. To avoid it - I filter it.
Warnings:
WARNING:Xst:1290 - Hierarchical block <FF> is unconnected in block <Demux>.
It will be removed from the design.
WARNING:Xst:1290 - Hierarchical block <filt> is unconnected in block <Demux>.
It will be removed from the design.
WARNING:Xst:2677 - Node <FF/Q> of sequential type is unconnected in block <Demux>.
WARNING:Xst:2677 - Node <filt/filtered_right_temp> of sequential type is unconnected in block <Demux>.
WARNING:Xst:2677 - Node <filt/filtered_left_temp> of sequential type is unconnected in block <Demux>.

Answer 1

Try adding some else clauses to your when clauses in your Demux.vhd.
led(0) <= '1' when counter = 10 else '0';
led(1) <= '1' when counter = 20 else '0';
led(2) <= '1' when counter = 30 else '0';
led(3) <= '1' when counter = 40 else '0';
led(4) <= '1' when counter = 50 else '0';
led(5) <= '1' when counter = 60 else '0';
led(6) <= '1' when counter = 70 else '0';
led(7) <= '1' when counter = 80 else '0';
Without these else clauses, the synthesizer may consider led to always be "11111111" and thus not depending on the inputs.