How to send a bit sequence at every clock to a std_logic signal in VHDL? - vhdl

Question

I have a project submission that requires me to design a pattern detector that detects and counts the occurrence of '11100' in the given input sequence. I have 2 codes. One is the actual code to generate the pattern and count it. the 2nd code is a testbench. I have very little experience with VHDL so please guide me.
I am trying to send a '11100' such that it goes in bit by bit automatically.
pattern_recogniser.vhd:
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
--Sequence detector for detecting the sequence "11100".
--Non overlapping type.
entity pattern_recogniser is
port( clk : in std_logic; --clock signal
reset : in std_logic; --reset signal
data : in std_logic; --serial bit sequence
-- det_vld : out std_logic; --A '1' indicates the pattern "1011" is detected in the sequence.
count : out integer);
end pattern_recogniser;
architecture Behavioral of pattern_recogniser is
type state_type is (A,B,C,D,E); --Defines the type for states in the state machine
signal state : state_type := A; --Declare the signal with the corresponding state type.
signal ct : integer;
begin
process(clk)
begin
if( reset = '0' ) then --resets state and output signal when reset is asserted.
-- det_vld <= '0';
ct <= 00000000;
state <= A;
elsif ( rising_edge(clk) ) then --calculates the next state based on current state and input bit.
case state is
when A => --when the current state is A.
-- det_vld <= '0';
if ( data = '0' ) then
state <= A;
else
state <= B;
end if;
when B => --when the current state is B.
if ( data = '0' ) then
state <= A;
else
state <= C;
end if;
when C => --when the current state is C.
if ( data = '0' ) then
state <= A;
else
state <= D;
end if;
when D => --when the current state is C.
if ( data= '0' ) then
state <= E;
else
state <= D;
end if;
when E => --when the current state is D.
if ( data = '0' ) then
state <= A;
-- det_vld <= '1';
ct <= ct + 1;
else
state <= B;
--Output is asserted when the pattern "11100" is found in the sequence.
end if;
when others =>
NULL;
end case;
end if;
end process;
process (ct)
begin
if(ct >=99) then
count <= 99; -- the count must show a "--" on the 7 segment display after it exceeds 99.
else
count <= ct;
end if;
end process;
end Behavioral;
and the second: testbench.vhd:
library ieee;
use ieee.std_logic_1164.all;
entity testbench is
port(count_t: out integer);
end testbench;
architecture behav of testbench is
component testset
port( ck : out std_logic;
rst : out std_logic;
dout : out std_logic);
end component;
component pattern_recogniser
port( clk : in std_logic; --clock signal
reset : in std_logic; --reset signal
data : in std_logic; --serial bit sequence
count : out integer);
end component;
signal clk_1 : std_logic := '0';
signal reset_1 : std_logic := '0';
signal data_1 : std_logic := '1';
signal count_s : integer := 0;
begin
--tb: testset port map (ck => clk_1, rst => reset_1, dout => data_1);
pat_rec : pattern_recogniser port map (clk => clk_1, reset => reset_1, data => data_1, count => count_s);
process(clk_1)
begin
clk_1 <= not clk_1 after 100 ps;
end process;
process is
begin
wait for 600 ps;
data_1 <= '0';
wait for 400 ps;
end process;
count_t <= count_s;
end behav;
I am not able to generate this sequence automatically using the ifs in the testbench. I have to generate it 110 times, then perform a rest and then 50 times more. How do I achieve this? Any help would be highly appreciated!!!