Comparing a long std_logic_vector to zeros - vhdl

Question

In simulation this works perfect. Is this is the best way of checking for
zeros for a synthesisable code. What would be the resources generated?
signal vector_slv : std_logic_vector(2048 downto 0);
...
if (vector_slv = (vector_slv'range => '0')) then
-- do something...
Is there any other optimal way to implement this solution considering h/w mapping (with optimal resource utilization).
I would be more interested in understanding the resources used.

Answer 1

There's no way that makes more or less sense for synthesis. Write the code that best expresses your intention.
If you are comparing a vector for all zeros, the following should all produce the same results, or you should file a serious bug against the tool!
signal vector_slv : std_logic_vector(2048 downto 0);
constant zeros : std_logic_vector(vector_slv'range) := (others => '0');
...
if vector_slv = (vector_slv'range => '0') then
-- do something...
if vector_slv = zeros then
-- do something...
if unsigned(vector_slv) = to_unsigned(0, vector_slv'length) then
-- do something...
and indeed for shorter vectors which fit in an integer:
if intvar = 0 then
will be exactly the same as any 32-bit vector comparison.
(BTW, note there is no need for parentheses around the if condition - VHDL is not C :)

Answer 2

If the range is available, as in your example code, then the suggestion
solution looks fine, and I would expect that synthesis tools are made to handle
constructions like this.
If the range is not available, then compare with zero can be made like:
library ieee;
use ieee.numeric_std.all;
...
if unsigned( {std_logic_vector expression of any length} ) = 0 then
-- do something...
I would expect that synthesis tools handle this the same was as for compare
with (vector_slv'range => '0').

Answer 3

As far as synthesis is concerned, yes, such simple constructs are usually optimized fairly well by the tool. The exact hardware layout of course depends on what your target is (FPGA, ASIC, ...).
My suggestion is to take a look at the synthesis result (e.g. Technology Map Viewer for Altera FPGAs). If synthesis clobbers it, you can manually convert it into a binary tree of comparisons with zero, taking into account the technology primitives you have available. This can be a lot more tricky than it sounds, though, especially for FPGAs (there's more than LUTs to play with there), and shouldn't be necessary with a decent tool.

Answer 4

You can also separate predicate and assignment by doing this :
signal is_zero : boolean;
signal vector_slv : std_logic_vector(2048 downto 0);
...
process(clk)
begin
if rising_edge(clk) then
is_zero <= vector_slv = (vector_slv'range => '0');
if is_zero then
...
end if;
end if;
end process;
This should improve your Timing very much. Take into account that the predicate 'is_zero' is now a delayed version of your original comparison !

Answer 5

You could use the unary operators, e.g.:
and
nand
or
nor
signal vector_slv: std_logic_vector(2048 downto 0);
...
if and vector_slv then
-- Do something for all 1...
elsif nand vector_slv then
-- Do something for at least one 0...
elsif or vector_slv then
-- Do something for at least one 1...
elsif nor vector_slv then
-- Do something for all 0...
end if;
Or you could use the functions defined in std_logic_1164, e.g.:
function "and" (l : STD_ULOGIC_VECTOR) return STD_ULOGIC;
function "nand" (l : STD_ULOGIC_VECTOR) return STD_ULOGIC;
function "or" (l : STD_ULOGIC_VECTOR) return STD_ULOGIC;
function "nor" (l : STD_ULOGIC_VECTOR) return STD_ULOGIC;
use ieee.std_logic_1164.all;
...
signal vector_slv: std_logic_vector(2048 downto 0);
...
if and(vector_slv) then
-- Do something for all 1...
elsif nand(vector_slv) then
-- Do something for at least one 0...
elsif or(vector_slv) then
-- Do something for at least one 1...
elsif nor(vector_slv) then
-- Do something for all 0...
end if;