so I'm new here and i have this problem
I have a project where I have to do a makefile
also I have 3 files , but let's take one at least
this is makefile
333.o: 333.c
gcc -c 333.c
clean: rm *.o hell
this is file I want to compile
#!/bin/bash
echo "enetered number $1 threshold $2"
Error c:1:2 invalid preprocessing directive #!
c:2: expected '=', ',',';','asm' or '_attribute' before string constant
what is wrong? can't figure out
thank you
You are trying to pound a nail with a screwdriver - you are using the wrong tool for the job.
You are trying to speak mandarin to (mono-lingual) frenchman - you are using the wrong language.
The contents of file you are trying to compile indicate that it is a shell script and not a c file. However when make sees that the file has a .c extension, it will try to compile it as if it were a c file, which its contents patently are not.
Before you go further I suggest you look at the differences between compiled and interpreted languages
bash is an interpreted language - there is no need for a compiler at all. Just give the file execute permissions and run it. bash will parse and interpret the file line by line and take the necessary actions
c is a compiled language. Before the source that defines a c program can run, it must be compiled. The compiler parses the .c files and generates binary object files, which contain machine instructions that your CPU directly understands.
To run your bash shell script, I would do the following:
mv 333.c 333.sh ; # rename to prevent any confusion
chmod +x 333.sh ; # give the bash script executable permissions
./333.sh 42 69 ; # run the script - give it some args, since your script references $1 and $2
Related
Hi I am new to creating makefile.
I have written the following commands in a makefile but they do not seem to execute when i type make in my terminal.
However, if i type the command separately in the terminal, it works.
I am trying to open a vivado project in this tcl file and do some spyglass analysis on it and save the result in a txt file.The tcl file also runs properly if executed separately.
I cd to my project folder where all the files- sources folder, project folder, makefile is present. I named it "makefile" so that i can execute it by typing make in the terminal.The makefile contents are as follows.
.PHONY : vivado_open
vivado_open:
$(info Hello Make)
bsub -Is -q i_soc_rh7 -R "rusage[mem=32000, temp=1GB] affinity[core(8):membind=localonly]" vivado -nolog -nojou -mode batch -source vivado.tcl
Here is the result from the terminal
$make
Hello Make
make: Nothing to be done for `vivado_open'.
Sorry, but there has to be something else going on here, that you haven't told us about. It's simply not possible for you to get that output if you typed make with that makefile.
You are using a variable, not a target named vivado_open, so make would never print nothing to be done for 'vivado_open'. It would say instead something like: nothing to be done for ../projectfiles/test.prj
Further, you didn't answer my question about TABs vs. spaces. If both the info and bsub lines are indented with TABs, there's no possible way that make would print Hello Make, without also printing the bsub command and trying to run it.
You must have another makefile in your directory, maybe named Makefile or GNUmakefile, that is being used instead of makefile. Or maybe you have an environment variable like MAKEFILES set which is causing other makefiles to be read.
If none of those appear to be true, you'll have to run make -d and see if you can figure out what's happening. That output is far too large to post to StackOverflow, so you'll have to try to read it yourself.
EDITED
OK, the problem is you're using spaces to indent your rules. In make, all recipe lines must be indented with a hard TAB character. Normal spaces don't mean anything special to make. Basically your makefile is interpreted as if you'd written this:
.PHONY : vivado_open
vivado_open:
$(info Hello Make)
bsub -Is -q i_soc_rh7 -R "rusage[mem=32000, temp=1GB] affinity[core(8):membind=localonly]" vivado -nolog -nojou -mode batch -source vivado.tcl
This is why you get this message "nothing to be done": you haven't actually defined a recipe for vivaldo_open, so there is literally nothing that make knows to do to update that target.
As an aside, normally you would get a syntax error for the bsub line because make doesn't know what that is. However, if you look carefully at your line you'll see that it contains a :. So, make is interpreting this as a set of targets and set of prerequisites, like this:
bsub ... affinity[core(8) : membind=localonly]" vivado ... vivado.tcl
(make doesn't care about quotes or other special characters like [] etc.)
So. Be sure you indent your recipe lines with TAB characters and you'll be fine. This is probably the single most common issue people have with makefiles.
I'm trying to create a shell script via cygwin that will automatically build an executable and run it. It's a very simple format of
#!/bin/bash
gcc test.c -o hello
./hello.exe
When I enter the 2nd and 3rd lines separately, everything works normally. However, if I save those 3 lines into a .sh file, the resulting .exe built has some extra character added in that will always throw off the last line.
hello.exe
I can't even replicate the file name because no tool, including the character map/MS word/other ASCII tools online will give me any result. Some online tool gave me the ASCII result , but as far as I can tell that doesn't correspond to anything meaningful. How can I avoid this problem in my shell script?
Very likely you have Windows linefeeds in the .sh file. Make sure you have Unix linefeeds.
I know nothing about shell scripting but something has come up and I need to be able to understand what two lines of code do so that I can modify a project I am working on
SDKROOT= make -C $TEMP_DIR -f $PROJECT_DIR/greg/Makefile VPATH=$PROJECT_DIR/greg || exit $?
$TEMP_DIR/greg -o $DERIVED_FILES_DIR/${INPUT_FILE_BASE}.m $INPUT_FILE_PATH
will you please explain what these two lines of code do... I know what the variables are and the path names but the rest of the syntax is confusing and foreign. Please help.
The first line:
SDKROOT= make -C $TEMP_DIR -f $PROJECT_DIR/greg/Makefile VPATH=$PROJECT_DIR/greg || exit $?
SDKROOT= sets the environment variable SDKROOT to nothing for the execution of the make command.
make is the build tool, and it's being run with the following options:
-C $TEMP_DIR: means run make in the directory $TEMP_DIR
-f $PROJECT_DIR/greg/Makefile specifies to make to use the Makefile in $PROJECT_DIR/greg
VPATH=$PROJECT_DIR/greg sets another variable, VPATH to $PROJECT_DIR/greg. VPATH specifies to make a search path for prerequisits.
|| exit $? means that if the make command fails the script should exit with the same error code as make, as $? means the return code of the last run program/command.
The second line:
$TEMP_DIR/greg -o $DERIVED_FILES_DIR/${INPUT_FILE_BASE}.m $INPUT_FILE_PATH
appears to be running the command $TEMP_DIR/greg with the option -o $DERIVED_FILES_DIR/${INPUT_FILE_BASE}.m and with some input from $INPUT_FILE_PATH. This looks like the program which may have been built from the previous line's make command, so it's hard to know exactly what it does.
EDIT
The SDKROOT is an environment variable used by XCode to say where the SDK it's using is installed. It will be a path like /Developer/SDKs/MacOSX"${HOST_VERSION}".sdk/ for instance. The value should be setup somewhere in XCode I imagine (I don't used xcode so can't be more helpful than that.). By doing SDKROOT= at the beginning of the command the value of SDKROOT will be nothing/blank. The reason for this is that the code being compiled will use resources which exist in the SDKROOT, rather than local ones; such resources may be classes, config or libraries for example.
I am doing a simple make file and iam getting the error too many arguments. I do not know what it is talking about
here is my code
project1: *.cpp *.h
g++ -o main *.cpp
here is what the terminal is saying
unixapps1:project1> project1: *.cpp *.h
project1:: Too many arguments.
I think the problems are two-fold:
You have an awfully large number of source files in your directory — so much so that the length of the names is too long for your shell.
You are mis-executing the makefile as if it was a shell script. The error message is what you'd get if you ran sh makefile and the project1: line was the first (non-blank, non-comment) line in it.
You need to run make or (if the makefile is named project1.mk) make -f project1.mk.
If I've guessed wrong (I hope I have), then you need to clarify what is prompt and what is command line in your question. Conventionally, you use $ as the shell prompt (for sh and relatives; % if you're using C shell or one of its relatives, or # if you're running as root — which you should not be doing if you are programming).
I have the following code, which is intended to run a java program on some input, and test that input against a results file for verification.
#!/bin/bash
java Program ../tests/test"$#".tst > test"$#".asm
spim -f test"$#".asm > temp
diff temp ../results/test"$#".out
The gist of the above code is to:
Run Program on a test file in another directory, and pipe the output into an assembly file.
Run a MIPS processor on that program's output, piping that into a file called temp.
Run diff on the output I generated and some expected output.
I made this shell script to help me automate checking of my homework assignment for class. I didn't feel like manually checking things anymore.
I must be doing something wrong, as although this program works with one argument, it fails with more than one. The output I get if I use the $# is:
./test.sh: line 2: test"$#".asm: ambiguous redirect
Cannot open file: `test0'
EDIT:
Ah, I figured it out. This code fixed the problem:
#!/bin/bash
for arg in $#
do
java Parser ../tests/test"$arg".tst > test"$arg".asm
spim -f test"$arg".asm > temp
diff temp ../results/test"$arg".out
done
It turns out that bash must have interpreted a different cmd arg for each time I was invoking $#.
enter code here
If you provide multiple command-line arguments, then clearly $# will expand to a list of multiple arguments, which means that all your commands will be nonsense.
What do you expect to happen for multiple arguments?