I'm trying to debug a custom Makefile from an open source C++ project. It's not recognizing any targets I make in the "Make Target" view.
I've triple checked the spelling of my targets and they're fine.
If I turn on "Generate Makefiles automatically" it will successfully call the "all" and "clean" targets, but no other targets.
I assume you are using Eclipse/CDT.
Don't choose automatically generate Makefile.
Instead, right click on the makefile and select Make Targets/create. Use the target names from the makefile. The targets will appear in the "Make Targets" window (Window/Show View/MakeTarget). You can then build any of the targets using the hammer symbol in the make targets window.
Glad that solved your problem. By the way you don't have to have the make file in the same location as your source files. Here is an example where we use a make file in one directory that uses cd to run make files in other directories:
all: subsystems
subsystems:
#cd Efficiency && $(MAKE)
#cd List && $(MAKE)
#cd Map && $(MAKE)
#cd Set && $(MAKE)
#cd UsingSTLEfficiently && $(MAKE)
#cd VectorAndArray && $(MAKE)
Related
I'm trying to clone a repository from git and compile it locally. The relevant part of the Makefile is pasted below.
BUILDDIR = $(PWD)/build
# rest of the Makefile
...
all: release
release: $(BUILDDIR)/buildr/Makedir $(BUILDDIR)/depqbf
$(BUILDDIR)/buildr/Makedir:
mkdir -p $(BUILDDIR)/buildr
$(BUILDDIR)/depqbf:
cd $(BUILDDIR); rm -rf depqbf; git clone git#github.com:lonsing/depqbf.git
cd $(BUILDDIR)/depqbf;./compile.sh
The problem is if I use rm -rf depqbf, the compilation process happens everytime I run make.
If I remove it, and perform make again
fatal: destination path 'depqbf' already exists and is not an empty directory.
Is it possible to only clone and compile if the directory is not present.
the compilation process happens everytime I run make
The target of your recipe:
$(BUILDDIR)/depqbf/depqbf:
cd $(BUILDDIR); rm -rf depqbf; git clone git#github.com:lonsing/depqbf.git
cd $(BUILDDIR)/depqbf;./compile.sh
is the file $(BUILDDIR)/depqbf/depqbf. You are telling Make that, if the target $(BUILDDIR)/depqbf/depqbf
does not exist, then Make is to make the target by running the commands:
cd $(BUILDDIR); rm -rf depqbf; git clone git#github.com:lonsing/depqbf.git
cd $(BUILDDIR)/depqbf;./compile.sh
But those commands never create a file called $(BUILDDIR)/depqbf/depqbf. They
never make the target.
So every time Make considers the target it will decide that it has to made, by
running those commands.
If you remove rm -rf depqbf, then when Make attempts the target:
fatal: destination path 'depqbf' already exists and is not an empty directory.
Naturally, because you cannot clone into an existing non empty-directory. This is
not connected with the fact that the recipe is always being run. It is always being run
because it never makes its target.
Your other recipe:
$(BUILDDIR)/buildr/Makedir:
mkdir -p $(BUILDDIR)/buildr
likewise is one that that never makes it target. The command:
mkdir -p $(BUILDDIR)/buildr
will never create the file $(BUILDDIR)/buildr/Makedir. I do not see the purpose
of this recipe, so I'll assume it is just supposed to create the file
$(BUILDDIR)/buildr/Makedir if it does not exist, for some reason.
Then this makefile will attempt to make the targets if and only if they don't exist:
Makefile
BUILDDIR := $(PWD)/build
.PHONY: all release
all: release
release: $(BUILDDIR)/buildr/Makedir $(BUILDDIR)/depqbf
$(BUILDDIR)/buildr/Makedir: | $(BUILDDIR)/buildr
touch $#
$(BUILDDIR)/depqbf: | $(BUILDDIR)
cd $(dir $#); git clone git#github.com:lonsing/depqbf.git
cd $#; ./compile.sh
$(BUILDDIR) $(BUILDDIR)/buildr:
mkdir -p $#
Useful references in The GNU Make manual:-
An Introduction to Makefiles
Phony Targets
Types of Prerequisites
Automatic Variables
I have a very simple makefile that I ported from Linux to Windows
it only goes inside subfolders and calls other makefiles
all:
$(MAKE) clean
#(cd apps; $(MAKE))
clean:
cd apps; $(MAKE) clean;
the problem is that I don't understand how the #(command1; command2; command3;) syntax works and I'm unable to make it work even with the simplest of commands
For instance
all:
dir
works fine and it outputs the contents of the directory (and I'm in the right one)
all:
cd apps; dir
Does not work, it outputs
cd apps; dir The system cannot find the path specified.
Even worse if I keep the parentheses:
all:
#(dir)
outputs
process_begin: CreateProcess(NULL, (dir), ...) failed. make (e=2): The
system cannot find the file specified.
Can somebody please point me to the proper documentation? I know it must be very simple but all the guesswork so far failed and the documentation is too huge to read it all. I tried but I couldn't find what I'm looking for
Thanks
In a fairly complex Makefile, I'd occasionally like to invoke certain rules only if a target does exist. For example, I may have created a local directory and used losetup to mount a file onto it. I'd like to leave the mountpoint and the directory open while working on them, but automatically close them before certain operations.
When it's time to package things up, I want to sync the mounted file, umount it, and then do something with the underlying file. Is there are way to invert the sense of a rule so that it executes only if a particular target is present?
How about something like:
target = $(wildcard somefile)
$(target): ; #echo build $#
.PHONY: $(target)
I've written a scons build chain form a little C project, but I'm afraid users won't like to be told "You should install SCons first. Besides, it's really cool!" (expecially my professor, as he's kind of from the old guard).
Is there a way I can set up a Makefile that will wrap scons, not requiring it to be installed on the target system?
After looking for such a solution some time ago, I ended up writing a Makefile for this purpose.
Because SCons also comes as a drop-in userspace package scons-local (see the download page), one can fetch in and run it. Here is a dissectioned and commented version of my Makefile, which I also uploaded as a gist.
all: get_scons
#$(SCONS_EXE)
↑ The default action depends on scons being available, and simply runs the scons command (set later in the script) (the # symbol prevents make from printing the command)
SCONS_VERSION=2.3.4
scons-local-%.tar.gz:
curl -L http://sourceforge.net/projects/scons/files/scons-local/$(SCONS_VERSION)/scons-local-$(SCONS_VERSION).tar.gz > scons-local-$(SCONS_VERSION).tar.gz
touch scons-local-$(SCONS_VERSION).tar.gz
scons-local: scons-local-$(SCONS_VERSION).tar.gz
mkdir -p scons-local
tar xzf scons-local-$(SCONS_VERSION).tar.gz --directory scons-local
touch scons-local
↑ Set up the rules for fetching the tarball and unpack it into the scons-local directory
NATIVE_SCONS=$(strip $(shell which scons 2>/dev/null))
ifeq ($(NATIVE_SCONS),)
SCONS_EXE=python2 ./scons-local/scons.py
get_scons: scons-local
#echo "Couldn't find an installation of SCons, using a local copy"
else
SCONS_EXE=$(NATIVE_SCONS)
get_scons:
#echo "Found SCons installation at $(SCONS_EXE)"
endif
↑ Look for the scons executable in the search path (using the which command): if it is available, set up the get-scons target to simply print it is available. If, instead, it is not available, create the get-scons target instructing it to depend on the scons-local target defined earlier.
clean:
$(SCONS_EXE) -c
rm -rf scons-local
rm -f scons-local-*.tar.gz
.PHONY: all clean get_scons
↑ Finally, set-up the clean target that delegates to scons and deletes the local installation afterwards. The .PHONY rule tells make that the following rules do not correspond to files being created.
At this point, one could add more proxy rules of the kind:
mytarget: get_scons
#$(SCONS_EXE) mytarget
Which will invoke scons with the corresponding target.
Hope this is useful, feel free to correct me in case there's something wrong (I'm actually not a Makefile expert, and I'm trying not to become one by using SCons instead :P )
I have a working makefile that builds with mingw32. Now i renamed that makefile to Makefile.w32 (source -> http://pastie.org/319964)
Now i have a Makefile with the following. The problem is, it does not build my source
all:
make mingw32
clean:
#echo "causes an infinite loop -> make mingw32 clean"
mingw32:
#echo "yeahhhhhhhhh"
make Makefile.w32
mingw32-clean:
#echo "mingw clean"
make Makefile.w32 clean
result:
> "make"
make mingw32
make[1]: Entering directory `/c/nightly/test'
yeahhhhhhhhh
make Makefile.w32
make[2]: Entering directory `/c/nightly/test'
make[2]: Nothing to be done for `Makefile.w32'.
make[2]: Leaving directory `/c/nightly/test'
make[1]: Leaving directory `/c/nightly/test'
It seems to me it doesn't like Makefile.w32 extension. I dont understand why it isn't building. It;s obviously getting to my "make Makefile.w32" line.
"make Makefile.w32" is looking for a target named Makefile.w32, not a make file by that name. To run make and tell it to read the make file "Makefile.w32", use the -f switch:
make -f Makefile.w32
Edit: Incidentally, why do you launch a separate instance of make in the "all" target, if all you want is for "all" to depend on the "mingw32" target in the same make file? It'd be better, IMHO, to declare it as a dependent target instead:
all: mingw32
Likewise with "clean" and "mingw32-clean":
clean: mingw32-clean
You can use cmake to generate makefiles. It should work on most platforms.