Make wildcard dependency No rule to make target needed by - makefile

Question

I am trying to build my targets with wildcards. Here is my Makefile:
BINARY = main
LDSCRIPT = stm32f4-discovery.ld
PREFIX ?= arm-none-eabi
CC = $(PREFIX)-gcc
LD = $(PREFIX)-gcc
OBJCOPY = $(PREFIX)-objcopy
CFLAGS += -Os -g \
-Wall -Wextra -Wimplicit-function-declaration \
-Wredundant-decls -Wmissing-prototypes -Wstrict-prototypes \
-Wundef -Wshadow \
-I$(TOOLCHAIN_DIR)/include \
-fno-common -mcpu=cortex-m4 -mthumb \
-mfloat-abi=hard -mfpu=fpv4-sp-d16 -MD -DSTM32F4
LDSCRIPT ?= $(BINARY).ld
LDFLAGS += --static -lc -lnosys -L$(TOOLCHAIN_DIR)/lib \
-L$(TOOLCHAIN_DIR)/lib/stm32/f4 \
-T$(LDSCRIPT) -nostartfiles -Wl,--gc-sections \
-mthumb -mcpu=cortex-m4 -mthumb -mfloat-abi=hard -mfpu=fpv4-sp-d16
OBJS += $(BINARY).o
all: images
images: $(BINARY).images
%.images: %.bin
##printf "*** $* images generated ***\n"
%.bin: %.elf
##printf " OBJCOPY $(*).bin\n"
$(Q)$(OBJCOPY) -Obinary $(*).elf $(*).bin
%.elf: $(OBJS) $(LDSCRIPT) $(TOOLCHAIN_DIR)/lib/libopencm3_stm32f4.a
##printf " LD $(subst $(shell pwd)/,,$(#))\n"
$(Q)$(LD) -o $(*).elf $(OBJS) -lopencm3_stm32f4 $(LDFLAGS)
%.o: %.c Makefile
##printf " CC $(subst $(shell pwd)/,,$(#))\n"
$(Q)$(CC) $(CFLAGS) -o $# -c $<
clean:
$(Q)rm -f *.o
$(Q)rm -f *.d
$(Q)rm -f *.elf
$(Q)rm -f *.bin
-include $(OBJS:.o=.d)
When I make, I get the error:
make: *** No rule to make target `main.bin', needed by `main.images'. Stop.
I am trying to make a single image, so I can change each % to $(BINARY), and this works, but I would like to figure out why this isn't working.

Answer 1

You are likely missing a dependency somewhere down the chain.
Note: Some people forget that the "Makefile" itself, when placed on the dependency line - is also checked for existance. Double check that you haven't renamed it.
Like #MadScientist recommends, "make -d" will be your friend here. Use that to locate the rule/file that should have been found but was not.
I simplified your example (on Linux) and got the same type of error with:
Makefile:
all: main.out
%.out: %.elf
g++ $^ -o $#
%.elf: %.obj
mv $^ $#
%.obj: %.cpp Makefile
g++ -c $^ -o $#
Create main.cpp, see it work, then rename main.cpp to something else that it can't find, run again, see it fail.
Now rename the Makefile itself, see the same failure.