VHDL or verilog SR latch - vhdl

Question

I'm trying to program my NEXYS2 board with a SR latch with NAND gates with an enable signal C. My inputs are (S, R, C) and outputs are (Q, Qbar). below is some code in VHDL that I tried but keep getting errors. also the schematics are below if that helps anyone to understand my question. if you know it in verilog that's okay too.
Thank you in advance
process(S,R,C,Q,Qbar)
begin
if (C = '1') then
Q <= (R nand Qbar);
Qbar <= (S nand Q);
end if;
end process;

Answer 1

First off, your implementation of your schematic is incorrect: R should be
~S, and S should be ~R. try tracing the logic through with S or R equal to 1
when C is 1 - the outputs should set high.
Corrected Verilog (I've only got Altera & Verilog here):
module top(
input wire S, R, C,
output reg Q, Qbar);
always #(S, R, C, Q, Qbar)
if(C) begin
Q <= (~R & Q) | S;
Qbar <= (~S & Q) | R;
end
endmodule
This synthesises Ok on Altera, with 2 warnings along the lines of
Warning (10240): Verilog HDL Always Construct warning at test.v(5): inferring latch(es) for variable "Q", which holds its previous value in one or more paths through the always construct
and a warning from the timing analyser that it analysed two combinational
loops as latches. The technology view looks plausible, but you have got a
problem with this coding style, which could lead to issues.
The problem is that you explicitly code the only feedback paths, but you also
leave the synthesiser to infer a latch. Your code includes if(C = '1'), so the
synthesiser infers memory behaviour - a latch - when C is not 1. However, this
is pointless, since you're also telling it explicitly where the latch is with
your feedback paths. Don't do both; it's a mistake to assume that any
synthesiser is smart enough to figure out what you really meant. Here's a
version that leaves no doubt about what you want:
module top(
input wire S, R, C,
output wire Q, Qbar);
wire S2 = ~(C & S);
wire R2 = ~(C & R);
assign Q = ~(S2 & Qbar);
assign Qbar = ~(R2 & Q);
endmodule
This instead gives two 'Found combinational loop of 2 nodes' warnings, as
you'd expect. This also synthesises Ok, and the RTL/technology views look Ok,
at first sight.
Standard disclaimer: timing analsysers are not good at timing designs with
combinational loops. this will probably all just work if you're just playing
around, but if this is a real design you'll need to think hard about your
constraints, and whether the analyser has actually traced through your
feedback path (it probably hasn't). You'll need to do a timing sim with sdf
back-annotation to confirm that it actually works.

Answer 2

Your schematic is correct.
The problem is in your VHDL code, because you didn't specify the circuit's functionalities completely (note that the output values for c='0' were not defined), which causes the inference of latches (only registered circuits can be designed with incomplete specifications because then the resulting signals are stored in D-type flip-flops anyway).
You can do the following (among other alternatives):
entity sr_latch is
port (
s, r, c: in bit;
q, qbar: buffer bit);
end entity;
architecture sr_latch of sr_latch is
begin
q <= (s nand c) nand qbar;
qbar <= (r nand c) nand q;
end architecture