synchronous state machine VHDL - vhdl

Question

I am trying to design a synchronous state machine with one input X and one output Z
z is 1 only if x has no. of 1's mod 3=0
and even no. of 0's
anyways i prepared my state diagram
i tried to test bench the code on xillinix and print the signals to trace it
but its not jumping from state to state correctly as written in the code
any help appreciated
here is the output in the link thanks
http://pastebin.com/14e5ZkX4
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity machine is
Port ( X : in STD_LOGIC;
clk : in STD_LOGIC;
Z : out STD_LOGIC);
end machine;
architecture Behavioral of machine is
signal state,nextstate : integer range 0 to 5 := 0;
signal flag : integer range 0 to 5 := 0;
begin
--state 0 (even and mod3=0)
--state 1 (odd and mod3=0)
--state 2 (even and mod3=1)
--state 3 (odd and mod3=1)
--state 4 (even and mod3=2)
--state 5 (odd and mod3=2)
sequence:process(CLK)
begin
if rising_edge(CLK) then
report "prevstate"& integer'image(state);
report "x" & STD_LOGIC'image(X);
if X='0' then
case state is
when 0=>
nextstate<= 1;
when 1=>
nextstate<= 0;
when 2=>
nextstate<= 3;
when 3=>
nextstate<= 2;
when 4=>
nextstate<= 5;
when 5=>
nextstate<= 4;
end case;
--if x=1
else
case state is
when 0=>
flag<= 1;
nextstate<= 2;
when 1=>
nextstate<= 3;
when 2=>
nextstate<= 4;
when 3=>
nextstate<= 5;
when 4=>
nextstate<= 0;
when 5=>
nextstate<= 1;
end case;
end if;
-- report "flag"& integer'image(flag);
report "next state"& integer'image(nextstate);
state<=nextstate;
if state=1 then
z<='1';
else
z<='0';
end if;
end if;
end process;
end Behavioral;

Answer 1

Seems like a weird way to achieve what you want... very complicated and combines two separate tasks into one, making it very difficult to check (by eye) that everything is as it should be. I'm in favour of describing the solution as you described the problem.
Keep track of the two bits of information separately. Some sample code below, which is not complete, you'll have to combine it into a clocked process and ensure the reset is done.
Have an 'even' flag, and each time X is '0', toggle it. Make sure to reset it to zero.
if x = '1' then
even := not even;
end if;
Also have a counter and each time X is a '1', increment it. If it gets to 3, reset it to zero. And make sure it starts from zero after reset!
if x = '1' then
counter := counter + 1;
if counter = 3 then
counter := 0;
end if;
end if;
Then take the two and combine them to produce the output:
z <= '0';
if counter = 0 and even = '1' then
z <= '1';
end if;

Answer 2

Well, I'm new to VHDL, but I think there is one big problem.
You try to use standard sequential-'Programming'-patterns to describe hardware!
When describing hardware, you have to keep in mind, that hardware is concurrent.
Your FSM won't have the expected behavior, because you did't keep that in mind.
For example the nextstate calculation is done in a clocked process, which is okay,
but then there should be a concurrent signal assignment (outside of the process) for the state-signal.
The new values for nextstate-signals won't be available in the same process-cycle.
They will be assigned after the process is done. (Warning: It is true for signals only,
variables have some different behavior!)
I think a good VHDL book will teach you the basics...