My task is to take 2 inputs from keyboard which is numbers from 0 to 9 and to add them. Problem is in
STORING these numbers.i want to save first press(input no.) into "a" and second press(input no.) into
"b" but by using following code first press stores in both a and b. 2nd press is of no use. here
scan_code = scancode of the pressed button (output of keyboard interfacing code)
a = number in binary (for example if first time i press "1" then the code check the scancode and assign the binary value of "1" to a).
Any one who can help?
process (clk, scan_code, cin)
variable scancode1 : std_logic_vector (7 downto 0) := "00000000";
variable cin2 : std_logic_vector(2 downto 0);
begin
if(clk'event and clk = '1') then
scancode1 := scan_code;
a <= "0000";
b <="0000";
if (scancode1 = "00010110") then
a <= "0001";
elsif (scancode1 = "00011110") then
a <="0010";
elsif (scancode1 = "00100110") then
a <="0011";
elsif (scancode1 = "00100101") then
a <="0100";
elsif (scancode1 = "00101110") then
a <="0101";
elsif(scancode1 = "00110110") then
a <="0110";
elsif (scancode1 = "00111101") then
a <="0111";
elsif (scancode1 = "00111110") then
a <="1000";
elsif (scancode1 = "01000110") then
a <="1001";
elsif (scancode1 = "01000101") then
a <="0000";
end if;
if (scancode1 = "01010101") then --scancode for + sign
a <=a;
end if;
if (scancode1 = "00010110") then
b <="0001";
elsif (scancode1 = "00011110") then
b <="0010";
elsif (scancode1 = "00100110") then
b <="0011";
elsif (scancode1 = "00100101") then
b <="0100";
elsif (scancode1 = "00101110") then
b <="0101";
elsif(scancode1 = "00110110") then
b <="0110";
elsif (scancode1 = "00111101") then
b <="0111";
elsif (scancode1 = "00111110") then
b <="1000";
elsif (scancode1 = "01000110") then
b <="1001";
elsif (scancode1 = "01000101") then
b <="0000";
end if;
sum(0) <= a(0) xor b(0) xor cin;
cin2(0) := (a(0) and b(0)) or (cin and (a(0) xor b(0)));
sum(1) <= a(1) xor b(1) xor cin2(0);
cin2(1) := (a(1) and b(1)) or (cin2(0) and (a(1) xor b(1)));
sum(2) <= a(2) xor b(2) xor cin2(1);
cin2(2) := (a(2) and b(2)) or (cin2(1) and (a(2) xor b(2)));
sum(3) <= a(3) xor b(3) xor cin2(2);
cout <= (a(3) and b(3)) or (cin2(2) and (a(3) xor b(3)));
end if;
end process;
"a" and "b" are updating at the same time as you wrote it like that (same "scancodes" are checked for "a" and "b" on the same clockedge). think about using an event trigger like in the following example:
...
if reset='1' then
a<=(others => '0');
b<=(others => '0');
event_last<='0';
event_nr<=0;
elsif rising_edge(clk) then
event_last<=event;
-- trigger on "rising edge" of event
if event='1' and event_last='0' then
case event_nr is
-- first event is "a"
when 0 =>
event_nr<=1;
if (scancode1 = "00010110") then
a <= "0001";
...
-- second event is "b"
when others =>
event_nr<=0;
if (scancode1 = "00010110") then
b <= "0001";
...
end case;
...
...
Related
I'm working on an FSM for a quadrature encoder counter, to be used on the Arty A7 35 --- this is my first VHDL project, so I apologize if I am missing something very basic. I have an internal count signal that I decrement or increment in the FSM, but when I try to assign that signal via COUNT_OUT <= count, COUNT_OUT stays at zero, even though I have been able to observe the state changing. I do this assignment at the very end of the FSM process.
simulation outputs
Further, I am not able to observe "state", "next state", or "count" in simulation --- I would appreciate help on this as well as would be very useful. These signals do not show up in the "objects" window beside the scope either
My entity declaration is as follows:
entity GPIO_demo is
Port ( BTN : in STD_LOGIC;
z : in STD_LOGIC;
A : in STD_LOGIC;
B : in STD_LOGIC;
LED : out STD_LOGIC;
CLK : in STD_LOGIC;
UART_TXD : out STD_LOGIC;
COUNT_OUT : out unsigned(11 downto 0)
);
end GPIO_demo;
I define these relevant signals in architecture:
type state_type is (S00, S01, S10, S11);
signal state, next_state: state_type;
signal count: unsigned(11 downto 0) := (others=>'0');
My FSM is as follows:
SYNC_PROC: process(CLK)
begin
if rising_edge(CLK) then
if ( z='1' ) then
state <= S00;
count <= "000000000000";
else
state <= next_state;
end if;
end if;
end process;
NEXT_STATE_DECODE: process(state, A, B)
begin
case state is
when S00 =>
if(A = '0' and B = '1') then
count <= "000000000000";
next_state <= S01;
elsif(A = '1' and B = '0') then
count <= "000000000000";
next_state <= S10;
end if;
when S01 =>
if(A = '1' and B = '1') then
count <= "100000000000";
next_state <= S11;
elsif(A = '0' and B = '0') then
count <= "100000000000";
next_state <= S00;
end if;
when S11 =>
if(A = '1' and B = '0') then
count <= count - 1;
next_state <= S10;
elsif(A = '0' and B = '1') then
count <= count + 1;
next_state <= S01;
end if;
when S10 =>
if(A = '0' and B = '0') then
count <= count - 1;
next_state <= S00;
elsif(A = '1' and B = '1') then
count <= count + 1;
next_state <= S11;
end if;
end case;
COUNT_OUT <= count;
end process;
Any idea on why this output does not update?
I'm trying to read input from the keypad and I want the number entered by the user to persist on a 7 segment display until another key is pressed.
Currently, the 7 segment display output disappears when the key is released. How can I make the 7 segment display output persist?
This is my entire code :
ARCHITECTURE Behavioral OF keypad IS
SIGNAL t1, t2, t3, t4: STD_LOGIC_VECTOR (1 TO 4) := "1111";
SIGNAL curr : STD_LOGIC_VECTOR(1 TO 4) := "0111";
BEGIN
proc_1: PROCESS
BEGIN
WAIT UNTIL rising_edge(clk);
IF curr <= "0111" THEN t1<= row ;
curr <= "1011";
ELSIF curr <= "1011" THEN t2<= row ;
curr <= "1101";
ELSIF curr <= "1101" THEN t3<= row ;
curr <= "1110";
ELSIF curr <= "1110" THEN t4<= row ;
curr <= "0111";
ELSE
curr <= "0111";
END IF ;
END PROCESS ;
proc_2: PROCESS (t1, t2, t3, t4)
BEGIN
hit <= '1';
IF t1(1) = '0' THEN sevenseg <= "1001111" ; --1
ELSIF t1(2) = '0' THEN sevenseg <= "1001100" ; --4
ELSIF t1(3) = '0' THEN sevenseg <= "0001111" ; --7
ELSIF t1(4) = '0' THEN sevenseg <= "1111111" ; --*
ELSIF t2(1) = '0' THEN sevenseg <= "0010010" ; --2
ELSIF t2(2) = '0' THEN sevenseg <="0100100" ; --5
ELSIF t2(3) = '0' THEN sevenseg <= "0000000" ; --8
ELSIF t2(4) = '0' THEN sevenseg <= "0000001" ; --0
ELSIF t3(1) = '0' THEN sevenseg <= "0000110" ; --3
ELSIF t3(2) = '0' THEN sevenseg <= "0100000" ; --6
ELSIF t3(3) = '0' THEN sevenseg <= "0000100" ; --9
ELSIF t3(4) = '0' THEN sevenseg <= "1111111" ; --#
ELSIF t4(1) = '0' THEN sevenseg <= "0001000" ; --A
ELSIF t4(2) = '0' THEN sevenseg <= "1111111" ; --B
ELSIF t4(3) = '0' THEN sevenseg <= "0110001" ; --C
ELSIF t4(4) = '0' THEN sevenseg <= "1111111" ; --D
ELSE
hit <= '0';
END IF;
END PROCESS;
col <= curr ;
END Behavioral ;
I've produced this VHDL code and testing it with a VWF file seems that it works. But the finite state machine that my code produces (I can see it using the QUARTUS tool "state machine viewer") it seems to be wrong. In this FSM seems that in each state it is possible to reach any one else state.
According to my project goals I need a counter that counts from zero to nine and it changes its value according to the value of two input signals w0 and w1. If w0 and w1 are both zero, the counter attends in its current state, if w0 is 0 and w1 is 1 the counter increases by one, if w0 is 1 and w1 is 0 the counter increases by two, if w0 and w1 are both 1 the counter decrements by one. There are also a clock signal and a reset signal.
LIBRARY ieee;
USE ieee.std_logic_1164.all;
ENTITY counter IS
PORT(clk, reset :in std_logic;
w :in std_logic_vector(1 DOWNTO 0);
cont :out std_logic_vector(3 DOWNTO 0););
END;
ARCHITECTURE arch_counter OF counter IS
TYPE state IS (zero, one, two, three, four, five, six, seven, eight, nine);
SIGNAL numbCorr, numbFuture :state;
BEGIN
PROCESS(w, numbCorr)
BEGIN
CASE numbCorr IS
WHEN zero => IF w = "00" THEN numbFuture <= zero;
ELSIF w = "01" THEN numbFuture <= one;
ELSIF w = "10" THEN numbFuture <= two;
ELSIF w = "11" THEN numbFuture <= zero;
END IF;
cont <= "0000";
WHEN one => IF w = "00" THEN numbFuture <= one;
ELSIF w = "01" THEN numbFuture <= two;
ELSIF w = "10" THEN numbFuture <= three;
ELSIF w = "11" THEN numbFuture <= zero;
END IF;
cont <= "0001";
WHEN two => IF w = "00" THEN numbFuture <= two;
ELSIF w = "01" THEN numbFuture <= three;
ELSIF w = "10" THEN numbFuture <= four;
ELSIF w = "11" THEN numbFuture <= one;
END IF;
cont <= "0010";
WHEN three => IF w = "00" THEN numbFuture <= three;
ELSIF w = "01" THEN numbFuture <= four;
ELSIF w = "10" THEN numbFuture <= five;
ELSIF w = "11" THEN numbFuture <= two;
END IF;
cont <= "0011";
WHEN four => IF w = "00" THEN numbFuture <= four;
ELSIF w = "01" THEN numbFuture <= five;
ELSIF w = "10" THEN numbFuture <= six;
ELSIF w = "11" THEN numbFuture <= three;
END IF;
cont <= "0100";
WHEN five => IF w = "00" THEN numbFuture <= five;
ELSIF w = "01" THEN numbFuture <= six;
ELSIF w = "10" THEN numbFuture <= seven;
ELSIF w = "11" THEN numbFuture <= four;
END IF;
cont <= "0101";
WHEN six => IF w = "00" THEN numbFuture <= six;
ELSIF w = "01" THEN numbFuture <= seven;
ELSIF w = "10" THEN numbFuture <= eight;
ELSIF w = "11" THEN numbFuture <= five;
END IF;
cont <= "0110";
WHEN seven => IF w = "00" THEN numbFuture <= seven;
ELSIF w = "01" THEN numbFuture <= eight;
ELSIF w = "10" THEN numbFuture <= nine;
ELSIF w = "11" THEN numbFuture <= six;
END IF;
cont <= "0111";
WHEN eight => IF w = "00" THEN numbFuture <= eight;
ELSIF w = "01" THEN numbFuture <= nine;
ELSIF w = "10" THEN numbFuture <= nine;
ELSIF w = "11" THEN numbFuture <= eight;
END IF;
cont <= "1000";
WHEN nine => IF w = "00" THEN numbFuture <= nine;
ELSIF w = "01" THEN numbFuture <= nine;
ELSIF w = "10" THEN numbFuture <= nine;
ELSIF w = "11" THEN numbFuture <= eight;
END IF;
cont <= "1001";
END CASE;
END PROCESS;
PROCESS(clk)
BEGIN
IF (rising_edge(clk)) THEN
IF reset = '0' THEN numbCorr <= numbFuture ;
ELSE numbCorr <= zero;
END IF;
END IF;
END PROCESS;
END;
I think with this code is not possible that if the current state is "zero" the future state will be for example "seven" (from the FSM viewer seems that is possible). It is correct or I'm wrong?
this is the FSM produced by quartus (the numberState are in Italian because my original code was in italian to)
I am trying to simulate an elevator and as a result i get the error
ERROR:Xst:827 = Signal count cannot be synthesized, bad synchronous description
I am following the code from this source [https://www.youtube.com/watch?v=i03_-NMwmDs] since mine is very similar,(i have 7 floors and two more elevators). At first i am working with the code mentioned on the video and later i am going to implement two more elevators to work together in this simulation.
Thanks in advance.
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity elevator is
port (clk: in std_logic;
sensors1: out std_logic:='0'; --sensors at each level for elevator 1
a1, a2, a3, a4, a5, a6, a7: out std_logic; -- for LED display at FPGA
insideopendoor, in1, in2, in3, in4, in5, in1up, in2up, in3up, in4up, in5up, in5down, in4down, in3down, in2down, in1down: std_logic; -- input request for each floor
opendoor: out std_logic; -- from inside elevator
closedoor: out std_logic); -- from inside elevator
end elevator;
architecture sequence of elevator is
constant timedoorclose: integer := 3;
constant timedoorclosed: integer := 2;
constant time_nx_state: integer :=4;
signal demand: std_logic_vector(0 to 4) := "00000";
signal direction_of_elevator : integer range 0 to 2 := 0;
signal updownpassenger : std_logic := '0';
signal signalstatus: std_logic := '1';
type status is (L1, L2, L3, L4, L5);
signal pr_state, nx_state: status;
begin
main: process (clk, insideopendoor, in1, in2, in3, in4, in5, in1up, in2up, in3up, in4up, in5up, in5down, in4down, in3down, in2down, in1down)
variable digit1 : std_logic_vector (6 downto 0);
variable count : integer range 0 to (time_nx_state + timedoorclose + timedoorclosed);
variable bufferopendoor : std_logic;
variable position : integer range 0 to 4;
variable tempup : integer range 1 to 2 := 1;
variable tempdown : integer range -4 to 4;
begin
if (clk'event and clk='1') then
demand(0) <= demand(0) or in1 or in1up or in1down;
demand(1) <= demand(1) or in2 or in2up or in2down;
demand(2) <= demand(2) or in3 or in3up or in3down;
demand(3) <= demand(3) or in4 or in4up or in4down;
demand(4) <= demand(4) or in5 or in5up or in5down;
case pr_state is
when L1 => position := 0;
when L2 => position := 1;
when L3 => position := 2;
when L4 => position := 3;
when L5 => position := 4;
end case;
for i in 1 to 4 loop
if demand(i) ='1' then
tempup := i - position;
else null;
end if;
end loop;
for i in 3 downto 0 loop
bufferopendoor := '1';
closedoor <= '0';
count := 0;
end loop; --
elsif (updownpassenger = '1') then
if (count < timedoorclose) then
opendoor <= '1';
bufferopendoor := '1';
elsif count < (timedoorclose + timedoorclosed) then
opendoor <= '0';
bufferopendoor := '0';
else
closedoor <= '0';
end if;
--else null; ------
--end if; ------
-----------part main-----------------
count := count +1;
if insideopendoor = '1' then
opendoor<='1';
bufferopendoor :='1';
closedoor <= '0';
count := 0;
elsif (updownpassenger ='1') then
if (count < timedoorclose) then
opendoor <= '1';
bufferopendoor := '1';
closedoor <= '0';
elsif (count < (timedoorclose + timedoorclosed)) then
opendoor <= '0';
bufferopendoor := '0';
closedoor <= '1';
else
closedoor <= '0';
pr_state <= nx_state;
if signalstatus = '1' then
signalstatus <= '0';
else
signalstatus <= '1';
end if;
count := 0;
end if;
else null; --
end if;--
case nx_state is
when L1 =>
digit1 := "1111001";
if demand(0) = '1' then
demand(0) <= '0';
else null;
end if;
when L2 =>
digit1 := "0100100";
if demand(1) = '1' then
demand(1) <= '0';
else null;
end if;
when L3 =>
digit1 := "0110000";
if demand(3) = '1' then
demand(3) <= '0';
else null;
end if;
when L4 =>
digit1 := "0011001";
if demand(3) = '1' then
demand(3) <= '0';
else null;
end if;
when L5 =>
digit1 := "0010010";
if demand(4) = '1' then
demand(4) <= '0';
else null;
end if;
when others => null;
end case;
a1 <= digit1(0);
a2 <= digit1(1);
a3 <= digit1(2);
a4 <= digit1(3);
a5 <= digit1(4);
a6 <= digit1(5);
a7 <= digit1(6);
end if;
end process main;
step: process (pr_state, signalstatus)
begin
case pr_state is
--end if;
when L1 =>
if (demand(0)='1') then
nx_state <= pr_state;
updownpassenger <= '1';
else
updownpassenger <= '0';
if direction_of_elevator = 1 then
nx_state <=L2;
elsif direction_of_elevator = 2 then
nx_state <= pr_state;
else
nx_state <= pr_state;
end if;
end if;
when L2 =>
if (demand(1)= '1') then
nx_state <= pr_state;
updownpassenger <= '1';
else
updownpassenger <= '0';
if direction_of_elevator = 1 then
nx_state <= L3;
elsif direction_of_elevator = 2 then
nx_state <= L1;
else
nx_state <= pr_state;
end if;
end if;
when L3 =>
if (demand(2)= '1') then
nx_state <= pr_state;
updownpassenger <= '1';
else
updownpassenger <= '0';
if direction_of_elevator = 1 then
nx_state <= L4;
elsif direction_of_elevator = 2 then
updownpassenger <= '1';
else
updownpassenger <= '0';
if direction_of_elevator = 1 then
nx_state <= L5;
elsif direction_of_elevator = 2 then
end if;
end if;
end if;
when L5 =>
if (demand(4)='1') then
nx_state <= pr_state;
updownpassenger <= '1';
else
updownpassenger <= '0';
if direction_of_elevator = 1 then
nx_state <= L4;
elsif direction_of_elevator = 2 then
nx_state <= L1;
else
nx_state <= pr_state;
end if;
end if;
when others => null;
end case;
end process step;
end sequence;
Your code seems very mixed up. There is a specific reason why it won't synthesise: think carefully when the code immediately following this line here
elsif (updownpassenger = '1') then
will be executed. It will be executed following a positive edge or negative edge on any input in the sensitivity list, apart from clk where it will be executed only following a negative edge. How would you design logic with such behaviour? Well, your synthesiser can't do it, either.
Basically, you need to refactor your code. You need to split it into sequential and combinational processes. (Combinational logic is logic whose output depends only on it's input and thus is logic that contains no latches or flip-flops. Sequential logic is logic that contains latches or flip-flops, but will also usually contain some gates too. Do not use latches - they are not synchronous design.) Whilst there are many ways to code such processes, it is wise to be consistent by sticking to a template. Here are three templates, which if followed, will give you everything you need and will keep your VHDL coding life simple:
Here is the template for sequential logic with an asynchronous reset, which all synthesis tools should understand:
process(clock, async_reset) -- nothing else should go in the sensitivity list
begin
-- never put anything here
if async_reset ='1' then -- or '0' for an active low reset
-- set/reset the flip-flops here
-- ie drive the signals to their initial values
elsif rising_edge(clock) then -- or falling_edge(clock) or clk'event and clk='1' or clk'event and clk='0'
-- put the synchronous stuff here
-- ie the stuff that happens on the rising or falling edge of the clock
end if;
-- never put anything here
end process;
Here is the template for sequential logic without an asynchronous reset:
process(clock) -- nothing else should go in the sensitivity list
begin
-- never put anything here
if rising_edge(clock) then -- or falling_edge(clock) or clk'event and clk='1' or clk'event and clk='0'
-- put the synchronous stuff here
-- ie the stuff that happens on the rising or falling edge of the clock
end if;
-- never put anything here
end process;
And here is the corresponding template for a combinational process:
process(all inputs in the sensitivity list) -- an 'input' is a signal either on the LHS of an assignment or a signal that is tested
begin
-- combinational logic (with complete assignment and no feedback)
end process;
i have a problem with my code it supposed to count from 0 to 99 but the problem that i have is that the counter starts at "80" and the Left number only increments at 10 seconds so it repeats..
Something like this
Starts at: 80 81 82 83 84 04 05 06 07 08 09
My code is this:
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_unsigned;
-- pin 86 selector de display 1
-- pin 87 selec2 display
-- Seg A pin 85, Seg B 84, Seg C 83, D 82, E 81, F 78, Seg g pin 77, H 76
entity ContadorExamen is
port(
CLK : in std_logic; -- se le asigna el pin 12
--clk1hz : out std_logic ;-- se le asigna el pin 51
datos : out std_logic_vector (6 downto 0);
unidades : out std_logic;
decenas: out std_logic
);
end entity;
architecture BH_Examen2Parcial of ContadorExamen is
signal freq1 : integer range 0 to 5000 := 0;
signal freqDec : integer range 0 to 24999999 := 0;
signal freq100 : integer range 0 to 249999999 := 0;
signal tmp1 : std_logic := '0';
signal tmp100 : std_logic := '0';
signal tmpDec : std_logic := '0';
signal counterUnidades : integer range 0 to 10 := 0;
signal counterDecenas : integer range 0 to 10 := 0;
signal segDecenas : std_logic_vector(6 downto 0);
signal segUnidades : std_logic_vector(6 downto 0);
begin
process(CLK) is
begin
if(CLK'event and CLK = '1') then
if(freq1 >= 5000) then
freq1 <= 0;
tmp1 <= not tmp1;
else
freq1 <= freq1 + 1;
tmp1 <= tmp1;
end if;
if(freq100 >= 249999999) then
freq100 <= 0;
tmp100 <= not tmp100;
else
freq100 <= freq100 + 1;
tmp100 <= tmp100;
end if;
if(freqDec >= 24999999) then
freqDec <= 0;
tmpDec <= not tmpDec;
else
freqDec <= freqDec + 1;
tmpDec <= tmpDec;
end if;
end if;
end process;
-- principio de cambios en el programa
process(tmp1) is
begin
if(tmp1 = '1') then
unidades <= '0';
decenas <= '1';
datos <= segDecenas;
else
datos <= SegUnidades;
decenas <= '0';
unidades <= '1';
end if;
end process;
ParaContarUnidades:process(tmp100) is
begin
if (tmp100 = '1') then
if(counterUnidades = 0) then
segUnidades <= "0000001";
elsif (counterUnidades = 1 ) then
segUnidades <= "1001111";
elsif (counterUnidades = 2 ) then
segUnidades <= "0010010";
elsif (counterUnidades = 3 ) then
segUnidades <= "0000110";
elsif (counterUnidades = 4 ) then
segUnidades <= "1001100";
elsif (counterUnidades = 5 ) then
segUnidades <= "0100100";
elsif (counterUnidades = 6 ) then
segUnidades <= "1100000";
elsif (counterUnidades = 7 ) then
segUnidades <= "0001111";
elsif (counterUnidades = 8 ) then
segUnidades <= "0000000";
elsif (counterUnidades = 9) then
segUnidades <= "0001100";
else
segUnidades <= "1111111";
end if;
if(counterUnidades < 9) then
counterUnidades <= counterUnidades + 1;
else
counterUnidades <= 0;
end if;
end if;
end process;
ParaContarDecenas:process(tmpDec) is
begin
if (tmpDec = '1') then
if(counterDecenas = 0) then
segDecenas <= "0000001";
elsif (counterDecenas = 1 ) then
segDecenas <= "1001111";
elsif (counterDecenas = 2 ) then
segDecenas <= "0010010";
elsif (counterDecenas = 3 ) then
segDecenas <= "0000110";
elsif (counterDecenas = 4 ) then
segDecenas <= "1001100";
elsif (counterDecenas = 5 ) then
segDecenas <= "0100100";
elsif (counterDecenas = 6 ) then
segDecenas <= "1100000";
elsif (counterDecenas = 7 ) then
segDecenas <= "0001111";
elsif (counterDecenas = 8 ) then
segDecenas <= "0000000";
elsif (counterDecenas = 9) then
segDecenas <= "0001100";
else
segDecenas <= "1111111";
end if;
if(counterDecenas < 9) then
counterDecenas <= counterDecenas + 1;
else
counterDecenas <= 0;
end if;
end if;
end process;
end architecture;
A couple issues that you will want to look into:
Note that counterDecenas and counterUnidades should be in the sensitivity list of the processes that use them because (as written) you want your segUnidades and segDecenas signals to update when tmpDec or tmp100 remain '1' but the counters change.
Moreover, you assign the counters to values based on themselves (such as counterDecenas <= counterDecenas + 1;) outside of a clocked process - this will produce a combinatorial loop. These need to be triggered only on clock edges.
Beyond that, it isn't clear what this entity is supposed to do. You say it is supposed to count from 0 to 99, but this clearly does more than the 1-liner that it would take to implement what you've described the desired functionality to be.