I am trying to implement 32x32 Register File in VHDL. I have been struggling with this issue for a while... More specifically, I get the following error when I try to compile the code:
HDLParsers:164 - "//vmware-host/shared folders/Shared from MAIN/decoder.vhd" Line 26. parse error, unexpected STRING_LITERAL, expecting PIPE or ROW
I have tried variety of different solutions and none of them worked.
I am placing all the entities as they appear in the top level system.
The top level system:
library IEEE;
use IEEE.STD_LOGIC_1164.all;
library work;
use work.array_pkg.all;
entity GenRegisters is
port( Rd_Data : in std_logic_vector(31 downto 0);
Rs, Rt, Rd : in std_logic_vector(4 downto 0);
Reg_Write : in std_logic; -- enable
Rs_Output: out std_logic_vector(31 downto 0);
Rt_Output: out std_logic_vector(31 downto 0);
CLK, RESET : in std_logic -- clock and reset
);
end GenRegisters;
architecture Behavioural of GenRegisters is
signal decoder_out : std_logic_vector(31 downto 0);
signal DOUT: std_logic_vector(31 downto 0);
-- component declaration
component Register32
port (
DIN : in std_logic_vector(31 downto 0); -- system inputs
DOUT : out std_logic_vector(31 downto 0); -- system outputs
ENABLE : in std_logic_vector (0 downto 0); -- enable
CLK, RESET : in std_logic -- clock and reset
);
end component; -- end component;
-- component declaration
component Mux32t5
port (
Registers : in array2d; -- system inputs
Rselect : in std_logic_vector(4 downto 0);
Rout : out std_logic_vector(31 downto 0) -- system outputs
);
end component; -- end component;
-- component declaration
component decoder
port (
enable : in std_logic; -- enable
binary_in: in std_logic_vector(4 downto 0); -- system inputs
decoder_out: out std_logic_vector(31 downto 0) -- system outputs
);
end component; -- end component;
begin
-- VHDL Generalte allows you to replicate components, see hep
Decoder_1: decoder
port map(Reg_write, Rd, decoder_out);
GEN_ADD: for I in 0 to 31 generate
Register32D:Register32 port map
(Rd_Data, DOUT, decoder_out(I), CLK, RESET); -- :)
end generate GEN_ADD;
Mux_Rt: Mux32t5
port map(Register32D, Rt, Rt_Output);
Mux_Rs: Mux32t5
port map(Register32D, Rs, Rs_Output);
end Behavioural;
Decoder entity:
-------------------------------------------------------
-------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
entity decoder is
port(
enable :in std_logic; -- Enable for the decoder
binary_in :in std_logic_vector (4 downto 0); -- 5-bit Input
decoder_out :out std_logic_vector (31 downto 0) -- 32-bit Output
);
end decoder;
architecture Behavioural of decoder is
begin
process (enable, binary_in)
begin
decoder_out <= X"00000000";
if (enable = '1') then
case (binary_in) is
when 5x"00" => decoder_out <= X"00000001";
when 5x"01" => decoder_out <= X"00000002";
when 5x"02" => decoder_out <= X"00000004";
when 5x"03" => decoder_out <= X"00000008";
when 5x"04" => decoder_out <= X"00000010";
when 5x"05" => decoder_out <= X"00000020";
when 5x"06" => decoder_out <= X"00000040";
when 5x"07" => decoder_out <= X"00000080";
when 5x"08" => decoder_out <= X"00000100";
when 5x"09" => decoder_out <= X"00000200";
when 5x"0A" => decoder_out <= X"00000400";
when 5x"0B" => decoder_out <= X"00000800";
when 5x"0C" => decoder_out <= X"00001000";
when 5x"0D" => decoder_out <= X"00002000";
when 5x"0E" => decoder_out <= X"00004000";
when 5x"0F" => decoder_out <= X"00008000";
when 5x"10" => decoder_out <= X"00010000";
when 5x"11" => decoder_out <= X"00020000";
when 5x"12" => decoder_out <= X"00040000";
when 5x"13" => decoder_out <= X"00080000";
when 5x"14" => decoder_out <= X"00100000";
when 5x"15" => decoder_out <= X"00200000";
when 5x"16" => decoder_out <= X"00400000";
when 5x"17" => decoder_out <= X"00800000";
when 5x"18" => decoder_out <= X"01000000";
when 5x"19" => decoder_out <= X"02000000";
when 5x"1A" => decoder_out <= X"04000000";
when 5x"1B" => decoder_out <= X"08000000";
when 5x"1C" => decoder_out <= X"10000000";
when 5x"1D" => decoder_out <= X"20000000";
when 5x"1E" => decoder_out <= X"40000000";
when 5x"1F" => decoder_out <= X"80000000";
when others => decoder_out <= X"00000000";
end case;
end if;
end process;
end Behavioural;
Register32:
-------------------------------------------------------
-------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.all;
entity Register32 is
port (
DIN : in std_logic_vector(31 downto 0); -- system inputs
DOUT : out std_logic_vector(31 downto 0); -- system outputs
ENABLE : in std_logic_vector(0 downto 0);
CLK, RESET : in std_logic -- clock and reset
);
end Register32;
architecture Behavioural of Register32 is
begin
process(CLK,RESET)
begin -- process
-- activities triggered by asynchronous reset (active high)
if RESET = '1' then DOUT <= "00000000000000000000000000000000";
-- activities triggered by rising edge of clock
elsif CLK'event and CLK = '1' then
if ENABLE='1' then DOUT <= DIN;
else null;
end if;
end if;
end process;
end Behavioural;
MUX_Rt:
-------------------------------------------------------
-------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
library work;
use work.array_pkg.all;
-- define inputs and outputs
entity Mux32t5 is
port(
Registers : in array2d;
RSelect : in std_logic_vector(4 downto 0);
Rout : out std_logic_vector(31 downto 0) );
end Mux32t5;
architecture Behavioural of Mux32t5 is
begin
with Rselect select
Rout <= Registers(0) when 5X"00",
Registers(1) when 5X"01",
Registers(2) when 5X"02",
Registers(3) when 5X"03",
Registers(4) when 5X"04",
Registers(5) when 5X"05",
Registers(6) when 5X"06",
Registers(7) when 5X"07",
Registers(8) when 5X"08",
Registers(9) when 5X"09",
Registers(10) when 5X"0A",
Registers(11) when 5X"0B",
Registers(12) when 5X"0C",
Registers(13) when 5X"0D",
Registers(14) when 5X"0E",
Registers(15) when 5X"0F",
Registers(16) when 5X"10",
Registers(17) when 5X"11",
Registers(18) when 5X"12",
Registers(19) when 5X"13",
Registers(20) when 5X"14",
Registers(21) when 5X"15",
Registers(22) when 5X"16",
Registers(23) when 5X"17",
Registers(24) when 5X"18",
Registers(25) when 5X"19",
Registers(26) when 5X"1A",
Registers(27) when 5X"1B",
Registers(28) when 5X"1C",
Registers(29) when 5X"1D",
Registers(30) when 5X"1E",
Registers(31) when 5X"1F",
X"0000" when others;
end Behavioural;
MUX_Rs:
-------------------------------------------------------
-------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
library work;
use work.array_pkg.all;
-- define inputs and outputs
entity Mux32t5 is
port(
Registers : in array2d;
RSelect : in std_logic_vector(4 downto 0);
Rout : out std_logic_vector(31 downto 0) );
end Mux32t5;
architecture Behavioural of Mux32t5 is
begin
with Rselect select
Rout <= Registers(0) when 5X"00",
Registers(1) when 5X"01",
Registers(2) when 5X"02",
Registers(3) when 5X"03",
Registers(4) when 5X"04",
Registers(5) when 5X"05",
Registers(6) when 5X"06",
Registers(7) when 5X"07",
Registers(8) when 5X"08",
Registers(9) when 5X"09",
Registers(10) when 5X"0A",
Registers(11) when 5X"0B",
Registers(12) when 5X"0C",
Registers(13) when 5X"0D",
Registers(14) when 5X"0E",
Registers(15) when 5X"0F",
Registers(16) when 5X"10",
Registers(17) when 5X"11",
Registers(18) when 5X"12",
Registers(19) when 5X"13",
Registers(20) when 5X"14",
Registers(21) when 5X"15",
Registers(22) when 5X"16",
Registers(23) when 5X"17",
Registers(24) when 5X"18",
Registers(25) when 5X"19",
Registers(26) when 5X"1A",
Registers(27) when 5X"1B",
Registers(28) when 5X"1C",
Registers(29) when 5X"1D",
Registers(30) when 5X"1E",
Registers(31) when 5X"1F",
X"0000" when others;
end Behavioural;
array_pkg:
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
package array_pkg is
TYPE array2d IS ARRAY(31 DOWNTO 0) OF STD_LOGIC_VECTOR(31 DOWNTO 0);
END array_pkg;
Can anyone provide some clues or solution for the problem please?
For your multiplexor you might consider a simpler alternate solution and replace the case statement with
use ieee.numeric_std.all ;
architecture Behavioural of Mux32t5 is
begin
ROut <= registers (to_integer(unsigned(binary_in))) ;
end Behavioural ;
Or alternately with the unsigned package (note this one requires VHDL-2008):
use ieee.numeric_std_unsigned.all ;
...
ROut <= registers (to_integer(binary_in)) ;
It looks like you're trying to use VHDL-2008 conventions for that case statement and the compiler is not happy with you. Try this in your decoder.vhd:
case (binary_in) is
when "00000" => decoder_out <= X"00000001";
when "00001" => decoder_out <= X"00000002";
when "00010" => decoder_out <= X"00000004";
when "00011" => decoder_out <= X"00000008";
Etc...
Related
I'm doing a BCD counter that can count up/down depending on the input signals. This is the requirement:
This is my VHDL code:
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.numeric_std.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
-- main
entity BCDcounter is
port(
D_in: in std_logic_vector(3 downto 0);
enable_in, load_in, up_in, clr_in, clk_50hz: in std_logic;
C_out: out std_logic;
LED0: out std_logic_vector(0 to 6)
);
end BCDcounter;
architecture Behavioral of BCDcounter is
signal Q_temp: std_logic_vector(3 downto 0);
signal clk_1hz: std_logic;
component Clock_Divider is
port ( clk,reset: in std_logic;
clock_out: out std_logic);
end component;
component BCD_counter is
port(
D: in std_logic_vector(3 downto 0);
enable, load, up, clr, clk: in std_logic;
Q: std_logic_vector(3 downto 0);
Cout: out std_logic
);
end component;
component led IS
PORT ( input : IN STD_LOGIC_VECTOR(3 downto 0);
output : OUT STD_LOGIC_VECTOR(6 downto 0));
end component;
begin
stage0: Clock_Divider port map(clk_50hz, clr_in, clk_1hz);
stage1: BCD_counter port map(D_in, enable_in, load_in, up_in, clr_in, clk_1hz, Q_temp, C_out);
stage2: led port map(Q_temp, LED0);
end Behavioral;
-- 1-digit BCD counter
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.numeric_std.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity BCD_counter is
port(
D: in std_logic_vector(3 downto 0);
enable, load, up, clr, clk: in std_logic;
Q: std_logic_vector(3 downto 0);
Cout: out std_logic
);
end BCD_counter;
architecture bhv of BCDcounter is
signal temp: std_logic_vector(3 downto 0);
begin
process(enable, load, up, clr, clk)
begin
if clr = '0' then
temp <= "0000";
elsif enable = '0' then
temp <= "0000";
elsif load = '1' then -- load = 1, enable = 1
temp <= D;
elsif(rising_edge(clk)) then -- load = 0, enable = 1
if up = '1' then -- count up
if temp = "1001" then
temp <= "0000";
Cout <= '1';
else
temp <= temp + 1;
end if;
else -- count down
if temp = "0000" then
temp <= "1001";
Cout <= '1';
else
temp <= temp - 1;
end if;
end if;
end if;
end process;
Q <= temp;
end bhv;
-- Clock Divider from 50MHz to 1Hz
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.numeric_std.ALL;
entity Clock_Divider is
port ( clk,reset: in std_logic;
clock_out: out std_logic);
end Clock_Divider;
architecture behavioral of Clock_Divider is
signal count: integer:=1;
signal tmp : std_logic := '0';
begin
process(clk,reset)
begin
if(reset='1') then
count <= 1;
tmp <= '0';
elsif(clk'event and clk='1') then
count <= count+1;
if (count = 25000000) then
tmp <= NOT tmp;
count <= 1;
end if;
end if;
clock_out <= tmp;
end process;
end behavioral;
-- LED 7 segments
LIBRARY ieee;
USE ieee.std_logic_1164.all;
ENTITY led IS
PORT ( input : IN STD_LOGIC_VECTOR(3 downto 0);
output : OUT STD_LOGIC_VECTOR(6 downto 0));
END led;
ARCHITECTURE behave OF led IS
BEGIN
PROCESS(input)
BEGIN
CASE input IS -- abcdefg
WHEN "0000" => output <= "0000001";
WHEN "0001" => output <= "1001111";
WHEN "0010" => output <= "0010010";
WHEN "0011" => output <= "0000110";
WHEN "0100" => output <= "1001100";
WHEN "0101" => output <= "0100100";
WHEN "0110" => output <= "0100000";
WHEN "0111" => output <= "0001111";
WHEN "1000" => output <= "0000000";
WHEN "1001" => output <= "0000100";
WHEN OTHERS => output <= "1111111";-- ALL OFF
END CASE;
END PROCESS;
END behave;
When compiling, I meet the error like this although I have already declared them above. Can anyone show me what problem with my code and how to fix this error? Thank you so much.
Your entity is called BCD_counter
entity BCD_counter is
but you have created the architecture for BCDCounter
architecture bhv of BCDcounter is
And it is quite correct, BCD_Counter has no object called clr or any of the other objects it lists.
Be careful when naming entities. I also recommend putting one entity/architecture pair per file, with the prefered method to name the file the same as the entity.
I'm trying to make a microprocessor architecture and I'm stuck. My accumulator, IR and PC don't seem to be working and I can't figure out why.
their outputs stay always undefined. I check the mapping and the other components of the mp they're are all correct the problem is somewhere in these registers.
------------------------------------------------------
-- ALU
------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
use work.up_pack.all;
entity alu is
port ( A, B : in std_logic_vector(15 downto 0);
alufs : in ALU_FCTS;
S : out std_logic_vector( 15 downto 0));
end alu;
architecture arch_alu of alu is
begin
S <= "0000000000000000"; -- sortie par défaut
process(A, B, alufs)
begin
case alufs is
when ALU_B => S <= B;
when ALU_SUB => S <= std_logic_vector(unsigned(B) - unsigned(A));
when ALU_ADD => S <= std_logic_vector(unsigned(B) + unsigned(A));
when ALU_B_INC => S <= std_logic_vector(unsigned(B) + 1);
when ALU_AND => S <= A and B;
when ALU_OR => S <= A or B;
when ALU_XOR => S <= A xor B;
when others => S <= "0000000000000000";
end case;
end process;
end arch_alu;
------------------------------------------------------
-- ACCUMULATER
------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
entity accumulator is
port( clk, raz, load : in std_logic;
data_in : in std_logic_vector(15 downto 0);
data_out : out std_logic_vector(15 downto 0);
acc15, accz : out std_logic );
end accumulator;
architecture arch_acc of accumulator is
signal q_reg : std_logic_vector(15 downto 0);
begin
process(clk)
begin
if rising_edge(clk) then
if raz='1' then q_reg <= (others => '0');
elsif load='1' then q_reg <= std_logic_vector(unsigned(q_reg) + unsigned(data_in)); end if;
end if;
end process;
data_out <= q_reg;
acc15 <= q_reg(15);
accz <= '1' when q_reg = "0000000000000000";
end arch_acc;
------------------------------------------------------
-- REGISTER PC
------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
entity pc_reg is
port( clk, raz, load : in std_logic;
data_in : in std_logic_vector(11 downto 0);
data_out : out std_logic_vector(11 downto 0) );
end pc_reg;
architecture arch_pc_reg of pc_reg is
signal interne : std_logic_vector(11 downto 0);
begin
process(clk)
begin
if rising_edge(clk) then
if raz='1' then interne <= (others => '0');
elsif load='1' then interne <= data_in;
end if;
end if;
end process;
data_out <= interne;
end arch_pc_reg;
------------------------------------------------------
-- IR (Instruction Register)
------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
use work.up_pack.all;
entity ir_reg is
port( clk, raz, load : in std_logic;
data_in : in std_logic_vector(15 downto 0);
data_out : out std_logic_vector(11 downto 0);
opcode : out OPCODE);
end ir_reg;
architecture arch_ir_reg of ir_reg is
signal interne : std_logic_vector(3 downto 0);
begin
process(clk)
begin
if rising_edge(clk) then
if raz='1' then data_out <= (others => '0');
elsif load='1'
then
data_out <= data_in(11 downto 0);
interne <= data_in(15 downto 12);
end if;
end if;
end process;
opcode <= OP_LDA when interne="0000" else
OP_STO when interne="0001" else
OP_ADD when interne="0010" else
OP_SUB when interne="0011" else
OP_JMP when interne="0100" else
OP_JGE when interne="0101" else
OP_JNE when interne="0110" else
OP_STP when interne="0111" else
OP_AND when interne="1000" else
OP_OR when interne="1001" else
OP_XOR when interne="1010" else
OP_LDR when interne="1011" else
OP_LDI when interne="1100" else
OP_STI when interne="1101" else
OP_JSR when interne="1110" else
OP_RET when interne="1111" else
OP_UNKNOWN;
end arch_ir_reg;
This is not an answer, but a testbench for you to work with. Your accumulator seems to work fine. I tested it with the testbench below. Use it as resource for writing testbenches for the rest of your modules. (You can write a test bench to test all the modules together or individually, just FYI)
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
entity tb_accumulator is
end tb_accumulator;
architecture behav of tb_accumulator is
signal clk : std_logic := '0';
signal raz : std_logic := '1';
signal load : std_logic := '0';
signal data_in : std_logic_vector(15 downto 0) := (others => '0');
signal data_out : std_logic_vector(15 downto 0) := (others => '0');
signal acc15 : std_logic := '0';
signal accz : std_logic := '0';
begin
--Assign values for signals being passed into accumulator.
clk <= not clk after 2.5 ns;
data_in <= "0000000000000001";
raz <= '0' after 90 ns; --You can do this instead of forcing a signal. Set at what times you want it to change values.
load <= '1' after 100 ns;
accu_inst : entity work.accumulator
port map(
clk => clk,
raz => raz,
load => load,
data_in => data_in,
data_out => data_out,
acc15 => acc15,
accz=> accz
);
end behav;
While all the code is perfectly compiled by ModelSim, I can't simulate it because of "Error loading design"
This is for a CRC encode and decode using a Linear Feedback Shift Register that uses D-FlipFlop as components. So the project is actually composed by the CRC box that contains the LFSR made by DFF.
library IEEE;
use IEEE.std_logic_1164.all;
entity CRC is
generic (
NBit : positive := 64;
poly : positive := 8
);
port(
clk :in std_logic;
reset :in std_logic;
md :in std_logic; --1 per sender, 0 per receiver
input :in std_logic_vector(Nbit-1 downto 0);
dout_s :out std_logic_vector(Nbit-1 downto 0);
dout_r :out std_logic_vector(Nbit-poly-1 downto 0)
);
end CRC;
architecture rtl of CRC is
component LFSR
generic (N : positive := 8);
port(
clk :in std_logic;
reset :in std_logic;
din :in std_logic;
dout :out std_logic_vector(N-1 downto 0);
ready :out std_logic
);
end component LFSR;
signal input_temp :std_logic_vector(Nbit-1 downto 0);
signal input_LFSR :std_logic;
signal output_LFSR :std_logic_vector(poly-1 downto 0);
signal ready_LFSR :std_logic;
constant crc_check :std_logic_vector(poly-1 downto 0):= (others => '0');
begin
LFSR_o: LFSR generic map (N => poly)
port map(
clk => clk,
reset => reset,
din => input_LFSR,
dout => output_LFSR,
ready => ready_LFSR
);
process (clk)
variable i : natural := 0;
begin
if (md = '1') then
input_temp(Nbit-1 downto poly)<=input(Nbit-1 downto poly);
input_temp(7 downto 0) <=(others =>'0');
if(rising_edge(clk)) then
input_LFSR <= input_temp(i);
i:= i+1;
if(ready_LFSR = '1') then
dout_s <= input(Nbit-1 downto 0) & output_LFSR;
end if;
end if;
elsif(md = '0') then
input_temp(Nbit-1 downto 0)<=input(Nbit-1 downto 0);
if(rising_edge(clk)) then
input_LFSR <= input_temp(i);
i:= i+1;
if(ready_LFSR = '1') then
--codice per il controllo
for t in 0 to poly-1 loop
if (output_LFSR(t)='1') then
dout_r <=(others =>'0');
exit;
elsif(t=poly-1 and output_LFSR(t)='0') then
dout_r <= input(Nbit-1 downto poly);
end if;
end loop;
end if;
end if;
end if;
end process;
end rtl;
here the LFSR
library IEEE;
use IEEE.std_logic_1164.all;
entity LFSR is
generic (NBit : positive := 8);
port(
clk :in std_logic;
reset :in std_logic;
din :in std_logic;
dout :out std_logic_vector(Nbit-1 downto 0);
ready :out std_logic
);
end LFSR;
architecture rtl of LFSR is
component DFC
port(
clk :in std_logic;
reset :in std_logic;
d :in std_logic;
crc :out std_logic;
q :out std_logic
);
end component DFC;
signal q_s : std_logic_vector (NBit-1 downto 0):= (others => '0');
signal crc_t : std_logic_vector (NBit-1 downto 0):= (others => '0'); --registro temporaneo su cui fare le operazioni
signal int_0 :std_logic := '0';
signal int_2 :std_logic := '0';
signal int_4 :std_logic := '0';
signal int_8 :std_logic := '0';
begin
int_0<= din xor q_s(7);
int_2<= q_s(1) xor q_s(7);
int_4<= q_s(3) xor q_s(7);
GEN: for i in 0 to Nbit-1 generate
FIRST: if i=0 generate
FF1: DFC port map (
clk => clk,
reset => reset,
d => int_0,
crc => crc_t(i), --funziona benissimo se metto dout(i)
q => q_s(i)
);
end generate FIRST;
THIRD: if i=2 generate
FF2: DFC port map (
clk => clk,
reset => reset,
d => int_2,
crc => crc_t(i),
q => q_s(i)
);
end generate THIRD;
FIFTH: if i=4 generate
FF4: DFC port map (
clk => clk,
reset => reset,
d => int_4,
crc => crc_t(i),
q => q_s(i)
);
end generate FIFTH;
INTERNAL: if i>0 and i<Nbit-1 and i/= 2 and i/=4 generate
FFI: DFC port map (
clk => clk,
reset => reset,
d => q_s(i-1),
crc => crc_t(i),
q => q_s(i)
);
end generate INTERNAL;
LAST: if i=Nbit-1 generate
FFN: DFC port map (
clk => clk,
reset => reset,
d => q_s(i-1),
crc => crc_t(i),
q => q_s(i)
);
end generate LAST;
end generate GEN;
process(clk)
variable t : natural := 0;
begin
--ready <= '0';
if(rising_edge(clk)) then
t:= t+1;
if t=24 then --per qualche ragione ho bisogno di 3 cicli di clock in più per arrivare al risultato ricercato
dout <= crc_t;
ready <='1';
end if;
end if;
end process;
end rtl;
here the DFF
library IEEE;
use IEEE.std_logic_1164.all;
entity DFC is
port(
clk :in std_logic;
reset :in std_logic;
d :in std_logic;
crc :out std_logic;
q :out std_logic
);
end DFC;
architecture rtl of DFC is
begin
process(clk, reset, d)
begin
if(reset = '1')then
q <= '0';
crc<= '0';
elsif (clk'event and clk='1') then
q <= d;
crc <= d;
end if;
end process;
end rtl;
and finally here the testbench for the CRC
library IEEE;
use IEEE.std_logic_1164.all;
entity CRC_tb is
end CRC_tb;
architecture testbench of CRC_tb is
component CRC is
generic (
NBit : positive := 20; --da rimettere a 64
poly : positive := 8
);
port(
clk :in std_logic;
reset :in std_logic;
md :in std_logic; --1 per sender, 0 per receiver
input :in std_logic_vector(Nbit-1 downto 0);
dout_s :out std_logic_vector(Nbit-1 downto 0);
dout_r :out std_logic_vector(Nbit-poly-1 downto 0)
);
end component;
constant T_CLK :time := 25 ns;
constant T_sim :time := 2000 ns;
signal sim_time :std_logic :='1';
constant M :integer :=20; --da rimettere a 64, Nbit
constant N :integer :=8; -- poly
signal clk_tb :std_logic :='0';
signal reset_tb :std_logic :='1';
signal md_tb :std_logic;
signal input_tb :std_logic_vector(M-1 downto 0);
signal dout_s_tb :std_logic_vector(M-1 downto 0);
signal dout_r_tb :std_logic_vector(M-N-1 downto 0);
begin
clk_tb <= (not(clk_tb)and sim_time) after T_CLK/2;
sim_time <= '0' after T_sim;
DUT_i : CRC
generic map (
Nbit => M,
poly => N
)
port map (
clk => clk_tb,
reset => reset_tb,
md => md_tb,
input => input_tb,
dout_s => dout_s_tb,
dout_r => dout_r_tb
);
input_process : process(clk_tb)
begin
if(rising_edge(clk_tb)) then
md_tb <= '1';
input_tb <= "10100111010000000000";
end if;
end process input_process;
end testbench;
I was expecting that everything went fine given that the CRC code doesn't do much if not creating connections. I'm very new to VHDL so I can't understand very well what
** Error: (vsim-3733) C:/Modeltech_pe_edu_10.4a/CRC2.0/CRC.vhd(50):
No default binding for component instance 'LFSR_o'.
The following component generic is not on the entity: N Time: 0 ns
Iteration: 0 Instance: /crc_tb/DUT_i/LFSR_o File:
C:/Modeltech_pe_edu_10.4a/CRC2.0/LFSR.vhd
Loading work.dfc(rtl)
Error loading design
means.
Thanks all for the answers.
I have this scheme
I have to write structural VHDL design for it.
So these are my components:
MUX:
library IEEE;
use IEEE.STD_LOGIC_1164.all;
entity mux is
port(
A : in STD_LOGIC_VECTOR(7 downto 0);
B : in STD_LOGIC_VECTOR(7 downto 0);
Sel : in bit;
Z : out STD_LOGIC_VECTOR(7 downto 0)
);
end mux;
architecture Beh of mux is
begin
Z <= A when Sel='1'else
B;
end Beh;
REG:
library IEEE;
use IEEE.STD_LOGIC_1164.all;
entity reg is
port(
C : STD_LOGIC;
LD : in bit;
Reg_in : in STD_LOGIC_VECTOR(7 downto 0);
R_out : out STD_LOGIC_VECTOR(7 downto 0)
);
end reg;
architecture Beh of reg is
begin
process (C)
begin
if (rising_edge (C)) then
if (LD = '1') then
R_out <= Reg_in;
end if;
end if;
end process;
end Beh;
TOP:
library IEEE;
use IEEE.STD_LOGIC_1164.all;
entity top is
port(
LDA, LDB, S1, S0 : in bit;
CLK : in STD_LOGIC;
X, Y : in STD_LOGIC_VECTOR(7 downto 0);
RB : out STD_LOGIC_VECTOR(7 downto 0)
);
end top;
architecture Beh of top is
signal regB_out : STD_LOGIC_VECTOR(7 downto 0);
signal regA_out : STD_LOGIC_VECTOR(7 downto 0);
signal mux1_res : STD_LOGIC_VECTOR(7 downto 0);
signal mux2_res : STD_LOGIC_VECTOR(7 downto 0);
begin
Mux1: entity mux(Beh)
port map
(
A => X,
B => regB_out,
Sel => S1,
Z => mux1_res
);
RegA: entity reg(Beh)
port map
(
LD => LDA,
C => CLK,
Reg_in => mux1_res,
R_out => regA_out
);
Mux2: entity mux(Beh)
port map
(
A => regA_out,
B => Y,
Sel => S0,
Z => mux2_res
);
RB<=regB_out;
RegB: entity reg(Beh)
port map
(
LD => LDB,
C => CLK,
Reg_in => mux2_res,
R_out => regB_out
);
end Beh;
I am not sure I wrote bind between RB, regB_out and B correctly. And in the waveform when S1 and S0 both equal 0, I get nonsence for 1 CLK period. Like on the screenshot at 600ns '01' on RB shouldn't be there. Can some one help me to find mistakes?
TestBench:
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_signed.all;
use IEEE.numeric_std.all;
ENTITY tbt is
END tbt;
ARCHITECTURE behavior OF tbt IS
COMPONENT TOP
PORT (
CLK : in STD_LOGIC;
LDA, LDB, S1, S0 : in bit;
X, Y : in STD_LOGIC_VECTOR(7 downto 0);
RB : out STD_LOGIC_VECTOR(7 downto 0)
);
END COMPONENT;
signal CLK_sig : std_logic;
signal LDA_sig, LDB_sig, S1_sig, S0_sig : bit :='0';
signal X_sig, Y_sig, RB_sig : std_logic_vector(7 downto 0):="00000000";
constant CLK_period : time := 100 ns;
constant s_per : time := 50 ns;
begin
-------------------------------------------------------------
uut: TOP PORT MAP (
CLK => CLK_sig,
LDA => LDA_sig,
LDB => LDB_sig,
S1 => S1_sig,
S0 => S0_sig,
X => X_sig,
Y => Y_sig,
RB=> RB_sig
);
-------------------------------------------------------------
CLK_process :process
begin
CLK_sig <= '0';
wait for CLK_period/2;
CLK_sig <= '1';
wait for CLK_period/2;
end process;
-------------------------------------------------------------
stim_proc: process
variable itertion_backwards : integer := 255;
variable itertion_forward : integer := 0;
begin
wait for CLK_period;
for itertion_forward in 0 to 254 loop
X_sig <= STD_LOGIC_VECTOR(TO_SIGNED(INTEGER(itertion_forward),8));
Y_sig <= STD_LOGIC_VECTOR(TO_SIGNED(INTEGER(itertion_backwards),8));
wait for CLK_period;
S1_sig<= not S1_sig;
wait for CLK_period;
S0_sig<= not S0_sig;
wait for CLK_period;
LDA_sig<= not LDA_sig;
wait for CLK_period;
LDB_sig<= not LDB_sig;
itertion_backwards := itertion_backwards - 1;
end loop;
wait;
end process;
end;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
entity fir_123 is
port( Clk : in std_logic; --clock signal
Xin : in signed(7 downto 0); --input signal
Yout : out signed(15 downto 0) --filter output
);
end fir_123;
architecture Behavioral of fir_123 is
component DFF is
port(
Q : out signed(15 downto 0); --output connected to the adder
Clk :in std_logic; -- Clock input
D :in signed(15 downto 0) -- Data input from the MCM block.
);
end component;
signal H0,H1,H2,H3 : signed(7 downto 0) := (others => '0');
signal MCM0,MCM1,MCM2,MCM3,add_out1,add_out2,add_out3 : signed(15 downto 0) := (others => '0');
signal Q1,Q2,Q3 : signed(15 downto 0) := (others => '0');
begin
--filter coefficient initializations.
--H = [-2 -1 3 4].
H0 <= to_signed(-2,8);
H1 <= to_signed(-1,8);
H2 <= to_signed(3,8);
H3 <= to_signed(4,8);
--Multiple constant multiplications.
MCM3 <= H3*Xin;
MCM2 <= H2*Xin;
MCM1 <= H1*Xin;
MCM0 <= H0*Xin;
--adders
add_out1 <= Q1 + MCM2;
add_out2 <= Q2 + MCM1;
add_out3 <= Q3 + MCM0;
--flipflops(for introducing a delay).
dff1 : DFF port map(Q1,Clk,MCM3);
dff2 : DFF port map(Q2,Clk,add_out1);
dff3 : DFF port map(Q3,Clk,add_out2);
--an output produced at every positive edge of clock cycle.
process(Clk)
begin
if(rising_edge(Clk)) then
Yout <= add_out3;
end if;
end process;
end Behavioral;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
entity dff is
port(`
Q : out signed(15 downto 0); --output connected to the adder
Clk :in std_logic; -- Clock input
D :in signed(15 downto 0) -- Data input from the MCM block.
);
end dff;
architecture Behavioral of dff is
signal qt : signed(15 downto 0) := (others => '0');
begin
Q <= qt;
process(Clk)
begin
if ( rising_edge(Clk) ) then
qt <= D;
end if;
end process;
end Behavioral;
When I run this code it compiles successfully error free syntax but I get several warning and because of that I am not getting desired result. I get Xin, Clkin & Yout undefined in simulation result. I tried in different ways but still I haven't resolved these warnings:
1) WARNING:Xst:1293 - FF/Latch has a constant value of 0 in
block . This FF/Latch will be trimmed during the optimization
process.
2) WARNING:Xst:1293 - FF/Latch has a constant value of
0 in block . This FF/Latch will be trimmed during the
optimization process.
3) WARNING:Xst:1293 - FF/Latch has a
constant value of 0 in block . This FF/Latch will be trimmed
during the optimization process.
4) WARNING:Xst:1896 - Due to other
FF/Latch trimming, FF/Latch has a constant value of 0 in
block . This FF/Latch will be trimmed during
There seems to be no problem with the code. The only thing that I thought could go wrong is the fact that the fir module doesn't have any reset. The code for fir is as follows:
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
entity fir_123 is
port( Clk : in std_logic; --clock signal
reset: in std_logic;
Xin : in signed(7 downto 0); --input signal
Yout : out signed(15 downto 0) --filter output
);
end fir_123;
architecture Behavioral of fir_123 is
component DFF is
port(
Q : out signed(15 downto 0); --output connected to the adder
Clk :in std_logic; -- Clock input
reset: in std_logic;
D :in signed(15 downto 0) -- Data input from the MCM block.
);
end component;
signal H0,H1,H2,H3 : signed(7 downto 0) := (others => '0');
signal MCM0,MCM1,MCM2,MCM3,add_out1,add_out2,add_out3 : signed(15 downto 0) := (others => '0');
signal Q1,Q2,Q3 : signed(15 downto 0) := (others => '0');
signal yout_int : signed(15 downto 0);
begin
--filter coefficient initializations.
--H = [-2 -1 3 4].
H0 <= to_signed(-2,8);
H1 <= to_signed(-1,8);
H2 <= to_signed(3,8);
H3 <= to_signed(4,8);
--Multiple constant multiplications.
MCM3 <= H3*Xin;
MCM2 <= H2*Xin;
MCM1 <= H1*Xin;
MCM0 <= H0*Xin;
--adders
add_out1 <= Q1 + MCM2;
add_out2 <= Q2 + MCM1;
add_out3 <= Q3 + MCM0;
--flipflops(for introducing a delay).
dff1 : DFF port map(Q1,Clk,reset,MCM3);
dff2 : DFF port map(Q2,Clk,reset,add_out1);
dff3 : DFF port map(Q3,Clk,reset,add_out2);
--an output produced at every positive edge of clock cycle.
registered_yout: process
begin
wait until rising_edge(clk);
if (reset = '1') then
yout_int <= (others => '0');
else
yout_int <= add_out3;
end if;
end process;
Yout <= yout_int;
end Behavioral;
I also added in reset for dff and the changed file looks like this:
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
entity dff is
port(
Q : out signed(15 downto 0); --output connected to the adder
Clk :in std_logic; -- Clock input
reset: in std_logic;
D :in signed(15 downto 0) -- Data input from the MCM block.
);
end dff;
architecture Behavioral of dff is
signal qt : signed(15 downto 0) := (others => '0');
begin
Q <= qt;
registered_qt : process
begin
wait until rising_edge(clk);
if (reset = '1') then
qt <= (others => '0');
else
qt <= D;
end if;
end process;
end Behavioral;
The testbench that I used is as follows:
library ieee;
use ieee.numeric_std.all;
use ieee.std_logic_1164.all;
entity tb is
end entity tb;
architecture test_bench of tb is
component fir_123 is
port( Clk : in std_logic;
reset : in std_logic;
Xin : in signed(7 downto 0);
Yout : out signed(15 downto 0)
);
end component fir_123;
constant clk_per : time := 8 ns;
signal clk: std_logic;
signal reset: std_logic;
signal Xin : signed(7 downto 0);
signal Yout : signed(15 downto 0);
begin
dft : component fir_123
port map (
Clk => clk,
reset => reset,
Xin => Xin,
Yout => Yout
);
Clk_generate : process --Process to generate the clk
begin
clk <= '0';
wait for clk_per/2;
clk <= '1';
wait for clk_per/2;
end process;
Rst_generate : process --Process to generate the reset in the beginning
begin
reset <= '1';
wait until rising_edge(clk);
reset <= '0';
wait;
end process;
Test: process
begin
Xin <= (others => '0');
wait until rising_edge(clk);
Xin <= (others => '1');
wait until rising_edge(clk);
Xin <= (others => '0');
wait for clk_per*10;
report "testbench finished" severity failure;
end process test;
end architecture test_bench;
I have checked the waveforms in a simulator and they all seem to be defined after the reset has been deasserted. The fact that Xin and Clk is undefined shows that there is something wrong with the testbench.