In a makefile, suppose I have two corresponding dependency and target lists, like this:
SRC = x.c y.c z.c
OBJS = x.o y.o z.o
Of course, my example is more complicated than this, but I want to know if it is possible to automatically create targets x.o, y.o, z.o depending on x.c, y.c, z.c respectively, like this:
x.o: x.c
y.o: y.c
z.o: z.c
I think the question was how to create rules for each of these targets, not how to create OBJS from SRC (although it's good to do that!).
The simplest way is to use the already-built-in rule in make that knows how to do it; you don't need to write your own. Just use:
all: $(OBJS)
and they'll all be created. You can control the compiler by setting the CC variable, the preprocessor flags by setting the CPPFLAGS variable, and the other compiler flags by setting the CFLAGS variable.
If you DO really want to write your own rule, then pattern rules will do that for you easily:
%.o : %.c
$(CC) $(CPPFLAGS) $(CFLAGS) -c -o $# $<
You can use substitution references:
OBJS = $(SRC:.c=.o)
or patsubst:
OBJS = $(patsubst %.c,%.o,$(SRC))
Related
I have two sets of source files in my project from which I need to generate object files.
SET_ONE = foo.o bar.o
SET_TWO = zerz.o zork.o
I want to pass add an extra option to CFLAGS when building the files in SET_ONE but not for those in SET_TWO. For example, I want:
> make -n
cc -c -DEXTRA_FLAG foo.c
cc -c -DEXTRA_FLAG bar.c
cc -c zerz.c
cc -c zork.c
...
Since the files have the same extension, the same rule applies to all of them, and I don't see a straightforward way to tweak CFLAGS for just the ones in one of the sets.
I could make custom rules for the files in SET_ONE:
foo.o : foo.c
$(CC) $(CFLAGS) -DEXTRA_FLAG foo.c
bar.o : bar.c
$(CC) $(CFLAGS) -DEXTRA_FLAG bar.c
but that leads to repetition, which will be harder to maintain. Is there a cleaner way to do this? It's probably been a decade since I hacked on a makefile.
There are a number of ways to do it. The most straightforward uses target-specific variables; add to your makefile:
$(SET_ONE): CFLAGS += -DEXTRA_FLAG
I am talking about this question where the person has updated his final solution with a makefile for the task. I am having a hard time understanding how it's done.
There is a rule:
$(OBJECTS): $(OBJDIR)/%.o : $(SRCDIR)/%.c
#$(CC) $(CFLAGS) -c $< -o $#
which I am unable to understand, but by intuition I know what it will be doing. Almost everything else is pretty much clear. Thanks!
This is a static pattern rule. The first field is a list of targets, the second is a target pattern which Make uses to isolate a target's "stem", the third is the prerequisite pattern which Make uses to construct the list of prerequisites.
Suppose you have
SRCDIR = src
OBJDIR = obj
OBJECTS = obj/foo.o obj/bar.o obj/baz.o
$(OBJECTS): $(OBJDIR)/%.o : $(SRCDIR)/%.c
#$(CC) $(CFLAGS) -c $< -o $#
If you make obj/foo.o, Make first identifies this rule as the one to use (since obj/foo.o is in the target list $(OBJECTS)), matches it against the target pattern obj/%.o and finds that the stem (the part matched by the wildcard %) is foo, then plugs that into the prereq pattern src/%.c and finds that the prerequisite is src/foo.c.
If you've also defined the variables
CC = gcc
CFLAGS = -thisflag -thatflag=something
Then the command in the rule becomes
#gcc -thisflag -thatflag=something -c src/foo.c -o obj/foo.o
(Note that $< is the first prerequisite and $# is the target name.)
In answer to your other question: Yes, a makefile can handle a dependency on a header file (x.h) so that if the header has been modified, Make will rebuild the target. No, this makefile doesn't do that. You can modify the makefile by hand, adding rules like
a.o: x.h
assuming you know what the inclusions actually are, or you can have the makefile do it automatically, which is an advanced technique you probably shouldn't attempt yet.
This line is explaining how to obtain the object files (.o) from the source (.c), it avoids having to repeat the line for each .c file.
The objects will be in OBJDIR and the sources in SRCDIR
$(CC) will contain the compiler, CFLAGS will contain the options for the compiler and -c tells gcc to compile the source into objects.
For example:
CC = gcc
CFLAGS = -g -Wall
can be converted into
gcc -g -Wall -c test.c -o test.o
I want to write a lot of tiny example programmes for one same library, each needs gcc $(OtherOpt) -o xxx -lthelibname xxx.c.
How to write a Makefile without dozens of tagret lines ?
Pattern rules are your friend for these situations. As long as your targets all match a predictable pattern -- and they do in this case, as they are all of the form "create foo from foo.c" -- you can write a single pattern rule that will be used for all of the targets:
OtherOpt=-Wall -g
all: $(patsubst %.c,%,$(wildcard *.c))
%: %.c
gcc $(OtherOpt) -o $# -lthelibname $<
Now you can either run simply make to build all your apps, or make appname to build a specific app. Here I've created a single pattern rule that will be used anytime you want to create something from something.c. I used the $# automatic variable, which will expand to the name of the output, and the $< variable, which will expand to the name of the first prerequisite, so that the command-line is correct regardless of the specific app being built. Technically you don't need the all line, but I figured you probably didn't want to always have to type in the name(s) of the apps you want to build.
Also, technically you can probably get away without having any of this makefile, because GNU make already has a built-in pattern rule for the %: %.c relationship! I mention this option only for completeness; personally, I prefer doing things the way I've shown here because it's a little bit more explicit what's going on.
%.o: %.c
gcc $(OtherOpt) -c -o $# -lthelibname $<
That compiles all .c files to their .o files (object code) of the same base name. Then in your actual target(s), you would include all necessary .o files as dependencies and use gcc $(OtherOpt) -o $# $^ -lthelibname, assuming I'm not misunderstanding how your build is set up.
Some versions of make also support the suffix rule .c.o to be ALMOST the same thing as %.o: %.c, but the suffix rules can't have any dependencies. Writing .c.o: foo.h tells make to compile "foo.h" to "foo.c.o" rather than requiring "foo.h" as a dependency of any file with a .c suffix as %.o: %.c foo.h would correctly do.
I learnd from http://sourceforge.net/projects/gcmakefile/
LDLIB = -lpthread
LDFLAGS = -Wl,-O1 -Wl,--sort-common -Wl,--enable-new-dtags -Wl,--hash-style=both $(LDLIB)
SRCDIRS =
SRCEXTS = .c .C .cc .cpp .CPP .c++ .cxx .cp
CFLAGS = -pipe -march=core2 -mtune=generic -Wfloat-equal \
#-Wall -pedantic
ifeq ($(SRCDIRS),)
SRCDIRS = .
endif
SOURCES = $(foreach d,$(SRCDIRS),$(wildcard $(addprefix $(d)/*,$(SRCEXTS))))
TARGET = $(addprefix bin/,$(basename $(SOURCES)))
all: $(TARGET)
ls -l $(TARGET)
bin/%: %.c dir
gcc $(CFLAGS) $(LDFLAGS) -o $# $<
dir:
#-mkdir bin
.PHONY : clean
clean:
-rm $(TARGET)
-rmdir bin
Our make file compiles .c source files with a static pattern rule like this:
OBJECTS = foo.o bar.o baz.o
$(OBJECTS): %.o: %.c
$(CC) $< $(C_OPTIONS) -c -o $#
I need to change one of the .c files to an Objective-C .m file. Invoking the compiler is the same for both source types, so I'd like to use the same rule and just tweak it to be more flexible. I'd rather not change the OPTIONS variable because it's also used for the linking step, etc.
Is there a way to make the rule above more flexible to accommodate both .c and .m files?
Thanks
We can add this either-or behavior to the list of things Make should be able to do easily, but isn't. Here's a way to do it, using "eval" to create a seperate rule for each object.
define RULE_template
$(1): $(wildcard $(basename $(1)).[cm])
endef
OBJECTS = foo.o bar.o baz.o
$(foreach obj,$(OBJECTS),$(eval $(call RULE_template,$(obj))))
$(OBJECTS):
$(CC) $< $(C_OPTIONS) -c -o $#
Note that this depends on the source files already existing before you run Make (foo.c or foo.m, but not both). If you're generating those sources in the same step, this won't work.
Here's a less clever, more robust method.
CPP_OBJECTS = foo.o bar.o
OBJECTIVE_OBJECTS = baz.o
OBJECTS = $(CPP_OBJECTS) $(OBJECTIVE_OBJECTS)
$(CPP_OBJECTS): %.o: %.c
$(OBJECTIVE_OBJECTS): %.o: %.m
$(OBJECTS):
$(CC) $< $(C_OPTIONS) -c -o $#
EDIT: corrected OBJECTS assignment, thanks to Jonathan Leffler.
Not really just copy to
$(OBJECTS): %.o: %.m
$(CC) $< $(C_OPTIONS) -c -o $#
The call to the same compiler is just a happy occasion. Normally you do not compile objective-c code with $(CC). That just feels strange.
But since you go in a harsh way, I won't post do-it-right solution, where you separate objective-C targets from C targets into two different $(OBJECTS)-like variables and make two rules (which you should really do). Too boring. Instead, take a hack!
OBJC_FILES:=$(subst $(wildcard *.m))
real_name = `(test -h $(1) && readlink $(1) ) || echo $(1)`
$(OBJECTS): %.o: %.c
$(GCC) $< $(C_OPTIONS) -c -o $(call real_name,$#)
$(OBJC_FILES): %.c: %.m
ln -s $< $#
And God help those who maintains it!
Btw, this obviously won't work if your m-files are generated.
all. Let's say I have a program that contains a long list of C source files, A.c, B.c, ...., Z.c, now I want to compile A.c, B.c with certain CFLAGS, and compile the rest part of source files with a different CFLAGS value.
How to write a Makefile to do the above described job? currently what I am doing in my Makefile is:
OBJ=[all other .o files here, e.g. D.o, D.o, E.o .... Z.o]
SPECIAL_OBJS=A.o B.o
all: $(OBJ) $(SPECIAL_OBJS)
$(SPECIAL_OBJS):
#echo [Compiling]: $(#:.o=.c)
$(CC) [SOME OTHER GCC OPTIONS HERE] $(CFLAGS) -c $(#:.o=.c) -o $#
%.o: %.c
#echo [Compiling]: $<
$(CC) $(CFLAGS) -o $# -c $<
It works, but looks just stupid/complicated. Can anyone help to point out what is the recommended way of doing this in Makefile? thanks!
Try using target-specific variables. A target-specific variable is declared like this:
TARGET: VAR := foo # Any valid form of assignment may be used ( =, :=, +=, ?=)
Now when the target named TARGET is being made, the variable named VAR will have the value "foo".
Using target-specific variables, you could do this, for example:
OBJ=[all other .o files here, e.g. D.o, D.o, E.o .... Z.o]
SPECIAL_OBJS=A.o B.o
all: $(OBJ) $(SPECIAL_OBJS)
$(SPECIAL_OBJS): EXTRA_FLAGS := -std=c99 # Whatever extra flags you need
%.o: %.c
#echo [Compiling]: $<
$(CC) $(CFLAGS) $(EXTRA_FLAGS) -o $# -c $<
The approach taken by linux kernel build system:
CFLAGS += $(CFLAGS-$#)
And then,
CFLAGS-A.o += -DEXTRA
CFLAGS-B.o += -DEXTRA
I can't answer the question for raw makefiles, but if you are willing to use automake it is trivial:
foo_CFLAGS = [options passed to CC only when building foo]