I am trying to run two 7 segments here, I have searched everywhere but could not find a satisfactory reply, how can I add 1 to a std_logic ? I tried the logic_arith library as well but nothing works. I read somewhere that i gotta use a (0 to 0) vector but umm i didn't really get that part. Here is my code
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
use ieee.std_logic_arith.all;
entity blah is
Port ( clk : in STD_LOGIC;
anode: out STD_LOGIC_VECTOR (3 downto 0);
segment: out STD_LOGIC_VECTOR (6 downto 0));
end blah;
architecture Behavioral of blah is
signal sel: STD_LOGIC;
signal r_anode: STD_LOGIC_VECTOR (3 downto 0);
begin
anode <= r_anode;
process (clk) begin
if (clk'event and clk = '1') then
sel <= sel+1;
end if;
end process;
process (sel) begin
case sel is
when '0' => r_anode <= "1110";
when '1' => r_anode <= "1101";
when others => r_anode <= "1111";
end case;
case r_anode is
when "1110" => segment <= "0100100";
when "1101" => segment <= "0010010";
when others => segment <= "1111111";
end case;
end process;
end;
And the error
ERROR:HDLParsers:808 - "E:/Xilinx Projects/blah/blah.vhd" Line 19. + can not have such operands in this context.
The sel is only a single bit, so adding 1 is like a not sel.
However, if sel is more bits in a std_logic_vector, you can add a
natural to std_logic_vector as unsigned with:
sel <= std_logic_vector(unsigned(sel) + 1);
Use only ieee.numeric_std, thus remove the ieee.std_logic_arith, since
std_logic_arith is not a standard library (Synopsys proprietary).
Related
I'm doing a BCD counter that can count up/down depending on the input signals. This is the requirement:
This is my VHDL code:
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.numeric_std.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
-- main
entity BCDcounter is
port(
D_in: in std_logic_vector(3 downto 0);
enable_in, load_in, up_in, clr_in, clk_50hz: in std_logic;
C_out: out std_logic;
LED0: out std_logic_vector(0 to 6)
);
end BCDcounter;
architecture Behavioral of BCDcounter is
signal Q_temp: std_logic_vector(3 downto 0);
signal clk_1hz: std_logic;
component Clock_Divider is
port ( clk,reset: in std_logic;
clock_out: out std_logic);
end component;
component BCD_counter is
port(
D: in std_logic_vector(3 downto 0);
enable, load, up, clr, clk: in std_logic;
Q: std_logic_vector(3 downto 0);
Cout: out std_logic
);
end component;
component led IS
PORT ( input : IN STD_LOGIC_VECTOR(3 downto 0);
output : OUT STD_LOGIC_VECTOR(6 downto 0));
end component;
begin
stage0: Clock_Divider port map(clk_50hz, clr_in, clk_1hz);
stage1: BCD_counter port map(D_in, enable_in, load_in, up_in, clr_in, clk_1hz, Q_temp, C_out);
stage2: led port map(Q_temp, LED0);
end Behavioral;
-- 1-digit BCD counter
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.numeric_std.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity BCD_counter is
port(
D: in std_logic_vector(3 downto 0);
enable, load, up, clr, clk: in std_logic;
Q: std_logic_vector(3 downto 0);
Cout: out std_logic
);
end BCD_counter;
architecture bhv of BCDcounter is
signal temp: std_logic_vector(3 downto 0);
begin
process(enable, load, up, clr, clk)
begin
if clr = '0' then
temp <= "0000";
elsif enable = '0' then
temp <= "0000";
elsif load = '1' then -- load = 1, enable = 1
temp <= D;
elsif(rising_edge(clk)) then -- load = 0, enable = 1
if up = '1' then -- count up
if temp = "1001" then
temp <= "0000";
Cout <= '1';
else
temp <= temp + 1;
end if;
else -- count down
if temp = "0000" then
temp <= "1001";
Cout <= '1';
else
temp <= temp - 1;
end if;
end if;
end if;
end process;
Q <= temp;
end bhv;
-- Clock Divider from 50MHz to 1Hz
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.numeric_std.ALL;
entity Clock_Divider is
port ( clk,reset: in std_logic;
clock_out: out std_logic);
end Clock_Divider;
architecture behavioral of Clock_Divider is
signal count: integer:=1;
signal tmp : std_logic := '0';
begin
process(clk,reset)
begin
if(reset='1') then
count <= 1;
tmp <= '0';
elsif(clk'event and clk='1') then
count <= count+1;
if (count = 25000000) then
tmp <= NOT tmp;
count <= 1;
end if;
end if;
clock_out <= tmp;
end process;
end behavioral;
-- LED 7 segments
LIBRARY ieee;
USE ieee.std_logic_1164.all;
ENTITY led IS
PORT ( input : IN STD_LOGIC_VECTOR(3 downto 0);
output : OUT STD_LOGIC_VECTOR(6 downto 0));
END led;
ARCHITECTURE behave OF led IS
BEGIN
PROCESS(input)
BEGIN
CASE input IS -- abcdefg
WHEN "0000" => output <= "0000001";
WHEN "0001" => output <= "1001111";
WHEN "0010" => output <= "0010010";
WHEN "0011" => output <= "0000110";
WHEN "0100" => output <= "1001100";
WHEN "0101" => output <= "0100100";
WHEN "0110" => output <= "0100000";
WHEN "0111" => output <= "0001111";
WHEN "1000" => output <= "0000000";
WHEN "1001" => output <= "0000100";
WHEN OTHERS => output <= "1111111";-- ALL OFF
END CASE;
END PROCESS;
END behave;
When compiling, I meet the error like this although I have already declared them above. Can anyone show me what problem with my code and how to fix this error? Thank you so much.
Your entity is called BCD_counter
entity BCD_counter is
but you have created the architecture for BCDCounter
architecture bhv of BCDcounter is
And it is quite correct, BCD_Counter has no object called clr or any of the other objects it lists.
Be careful when naming entities. I also recommend putting one entity/architecture pair per file, with the prefered method to name the file the same as the entity.
I have been searching this for a while and have not been able to replicate any posted solutions online so I was hoping some of you wonderful people could help me out.
I am creating an ALU. i have a two 32 bit inputs and one 32 bit output along with a 5 bit shamt and a 4 bit control signal. My code is as follows with the error location commented on.
library ieee;
use ieee.std_logic_1164.all;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
use ieee.numeric_std.all;
Entity mips_alu IS
PORT(ALUControl : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
inputA, inputB : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
shamt : IN STD_LOGIC_VECTOR(4 DOWNTO 0);
Zero : OUT STD_LOGIC;
ALU_Result : OUT STD_LOGIC_VECTOR(31 DOWNTO 0)
);
END mips_alu;
ARCHITECTURE behavior of mips_alu IS
BEGIN
PROCESS(ALUControl)
BEGIN
CASE ALUControl is
WHEN "0000" =>
ALU_Result <= inputA AND inputB;
WHEN "0001" =>
ALU_Result <= inputA OR inputB;
WHEN "0010" =>
ALU_Result <= inputA + inputB;
WHEN "0110" =>
ALU_Result <= inputA - inputB;
WHEN "0111" =>
IF (inputA < inputB) THEN
ALU_Result <= inputA;
END IF;
WHEN "1000" =>
ALU_Result <= shift_left(inputB, to_integer(unsigned(shamt)));
-- The line above is where i get my first error, The following lines will have the same issue
WHEN "1001" =>
ALU_Result <= shift_right(inputB, shamt);
WHEN "1010" =>
ALU_Result <= shift_left(inputB, inputA);
WHEN "1011" =>
ALU_Result <= shift_right(inputB, inputA);
WHEN "1100" =>
ALU_Result <= inputA NOR inputB;
WHEN "1101" =>
ALU_Result <= inputB(31 DOWNTO 16);
WHEN OTHERS =>
ALU_Result <= inputA;
END CASE;
END PROCESS;
END behavior;
The error I am getting says:
10511 VHDL Qualified Expression error at mips_alu.vhd(33): shift_left type specified in qualified expression must match std_logic_vector type that is implied for expression by context
I have tried several variations of this so if i am missing something please let me know, all help is appreciated as I am a bit of a novice to vhdl
In the numeric_std document you can find the function shift_left or shift_right. In both descriptions there you can see that function SHIFT_LEFT (ARG: UNSIGNED; COUNT: NATURAL) return UNSIGNED;. So you need to use casting of your std_logic_vector to unsigned.
In your case it will looks like:
ALU_Result <= std_logic_vector(shift_left(unsigned(inputB), to_integer(unsigned(shamt))));
end etc. for other lines where you use shift_left or shift_right function.
What I usually do is just this:
ALU_Result <= inputB(30 downto 0) & '0';
This stores is ALU_Result a vector equal to InputB shifted once.
In case you want to shift it more times you can use a loop.
while (i<to_integer(unsigned(shamt))) loop
ALU_Result <= inputB(30 downto 0) & '0';
i:=i+1;
end loop;
Its not an elegant solution but it will probably work.
For shifting to the right do:
ALU_Result <= '0' & inputB(31 downto 1);
Hi I have the program below that does what I want to do, shift 1 bit left or right depending on inputs s_right or s_enable. The numeric.std library contains shift operators and I want to start using them so I get a better grasp on the language but can find no good examples that show me the right way at using them
LIBRARY IEEE;
USE IEEE.std_logic_1164.all;
USE IEEE.numeric_std.all;
ENTITY S_REG8 IS
port ( clk, s_enable, s_right, ser_in : in std_logic;
ser_out : out std_logic
);
END ENTITY S_REG8;
ARCHITECTURE dflow OF S_REG8 IS
SIGNAL reg : std_logic_vector (7 DOWNTO 0); --7,6,5,4,3,2,1,0
SIGNAL selectors : std_logic_vector (1 DOWNTO 0);
BEGIN
SHIFT_REG:PROCESS (clk, s_enable, s_right)
BEGIN
selectors <= s_enable & s_right;
IF clk'EVENT and clk ='1' THEN
IF selectors <= "00" THEN
reg (7 DOWNTO 0) <= reg (7 DOWNTO 0);
ELSIF selectors <= "01" THEN
reg (7 DOWNTO 0) <= reg (7 DOWNTO 0);
ELSIF selectors <="10" THEN
reg (0) <= ser_in;
ser_out <= reg(7);
--reg <= std_logic_vector(shift_left(unsigned(reg), 1);
--SHIFT_LEFT (ARG: UNSIGNED; COUNT: NATURAL)
reg (7 DOWNTO 1) <= reg (6 DOWNTO 0);
ELSIF selectors <= "11" THEN
reg (7) <= ser_in;
ser_out <= reg(0);
--reg <= shift_right(std_logic_vector(reg));
reg (6 DOWNTO 0) <= reg (7 DOWNTO 1);
END IF;
END IF;
END PROCESS;
END ARCHITECTURE dflow;
Any help would be great thanks.
From package numeric_std, the body:
-- Id: S.1
function SHIFT_LEFT (ARG: UNSIGNED; COUNT: NATURAL) return UNSIGNED is
begin
if (ARG'LENGTH < 1) then return NAU;
end if;
return UNSIGNED(XSLL(STD_LOGIC_VECTOR(ARG), COUNT));
end SHIFT_LEFT;
-- Id: S.2
function SHIFT_RIGHT (ARG: UNSIGNED; COUNT: NATURAL) return UNSIGNED is
begin
if (ARG'LENGTH < 1) then return NAU;
end if;
return UNSIGNED(XSRL(STD_LOGIC_VECTOR(ARG), COUNT));
end SHIFT_RIGHT;
These call:
-----------------Local Subprograms - shift/rotate ops-------------------------
function XSLL (ARG: STD_LOGIC_VECTOR; COUNT: NATURAL) return STD_LOGIC_VECTOR
is
constant ARG_L: INTEGER := ARG'LENGTH-1;
alias XARG: STD_LOGIC_VECTOR(ARG_L downto 0) is ARG;
variable RESULT: STD_LOGIC_VECTOR(ARG_L downto 0) := (others => '0'); begin
if COUNT <= ARG_L then
RESULT(ARG_L downto COUNT) := XARG(ARG_L-COUNT downto 0);
end if;
return RESULT; end XSLL;
function XSRL (ARG: STD_LOGIC_VECTOR; COUNT: NATURAL) return STD_LOGIC_VECTOR
is
constant ARG_L: INTEGER := ARG'LENGTH-1;
alias XARG: STD_LOGIC_VECTOR(ARG_L downto 0) is ARG;
variable RESULT: STD_LOGIC_VECTOR(ARG_L downto 0) := (others => '0'); begin
if COUNT <= ARG_L then
RESULT(ARG_L-COUNT downto 0) := XARG(ARG_L downto COUNT);
end if;
return RESULT; end XSRL;
Where you find SHIFT_LEFT fills reg(0) with '0' and SHIFT_RIGHT fills reg(7) with '0'.
You had previously assigned ser_in to reg(7) and reg(0) respectively, those assignments would be lost (the last assignment in a sequence of statements wins).
So reverse the order of the assignments:
architecture fie of s_reg8 is
signal reg: std_logic_vector (7 downto 0);
signal selectors: std_logic_vector (1 downto 0);
begin
-- make process purely clock synchrnous
selectors <= s_enable & s_right;
-- ser_out multiplexer instead of flip flop:
ser_out <= reg(7) when s_right = '0' else
reg(0); -- when s_right = '1' else
-- 'X';
shift_reg:
process (clk)
begin
if rising_edge (clk) then -- immunity to metastability transitions
-- if clk'event and clk ='1' then
-- if selectors <= "00" then -- redundant
-- reg (7 downto 0) <= reg (7 downto 0);
-- if selectors <= "01" then -- redundant
-- reg (7 downto 0) <= reg (7 downto 0);
-- elsif selectors <= "10" then
if selectors = "10" then -- was elsif equality not
reg <= std_logic_vector(shift_left(unsigned(reg), 1));
-- also added missing right paren
reg (0) <= ser_in; -- change the order so this occurs
-- ser_out <= reg(7); -- no flip flop
-- reg <= std_logic_vector(shift_left(unsigned(reg), 1);
-- SHIFT_LEFT (ARG: UNSIGNED; COUNT: NATURAL)
-- reg (7 downto 1) <= reg (6 downto 0);
-- elsif selectors <= "11" then
elsif selectors = "11" then
reg <= std_logic_vector(shift_right(unsigned(reg),1));
-- missing distance, proper type conversion
reg (7) <= ser_in; -- change order so this assignment happens
-- ser_out <= reg(0); -- no flip flop
-- reg <= shift_right(std_logic_vector(reg));
-- reg (6 downto 0) <= reg (7 downto 1);
end if;
end if;
end process;
end architecture;
Notice this also gets rid of the ser_out flip flop using a 2:1 mux instead, get's rid of the superfluous 'hold' assignments to reg(7 downto 0), uses the rising_edge function for immunity to events from a metastability value on clk and moves the selectors assignment to a concurrent signal assignment, allowing the process to be purely clock synchronous.
With a testbench (for shift right only):
library ieee;
use ieee.std_logic_1164.all;
entity s_reg8_tb is
end entity;
architecture foo of s_reg8_tb is
signal clk: std_logic := '0';
signal s_enable: std_logic;
signal s_right: std_logic;
signal ser_in: std_logic;
signal ser_out: std_logic;
constant ser_in_val0: std_logic_vector (1 to 8) := x"B9";
constant ser_in_val1: std_logic_vector (1 to 8) := x"AC";
begin
CLOCK: -- clock period 20 ns
process
begin
wait for 10 ns;
clk <= not clk;
if now > 800 ns then -- automagically stop the clock
wait;
end if;
end process;
DUT:
entity work.s_reg8
port map (
clk => clk,
s_enable => s_enable,
s_right => s_right,
ser_in => ser_in,
ser_out => ser_out
);
STIMULUS:
process
begin
s_enable <= '1';
s_right <= '1';
for i in 1 to 8 loop
ser_in <= ser_in_val0(i);
wait for 20 ns; -- one clock period
end loop;
for i in 1 to 8 loop
ser_in <= ser_in_val1(i);
wait for 20 ns; -- one clock period
end loop;
for i in 1 to 8 loop -- so we get all val0 out
ser_in <= ser_in_val0(i);
wait for 20 ns; -- one clock period
end loop;
s_enable <= '0';
wait for 20 ns; -- one clock
wait;
end process;
end architecture;
We get:
Notice at this point we haven't tested s_enable nor s_right = '0', but SHIFT_RIGHT works. Will SHIFT_LEFT work?
The secret was assigning the serial in to reg(0) or reg(7) after the shift function.
Thanks for the detailed reply user1155120. I have used the description below to simulate the left and right shift of one bit through the register.
LIBRARY IEEE;
USE IEEE.std_logic_1164.all;
USE IEEE.numeric_std.all;
ENTITY S_REG8 IS
port ( clk, s_enable, s_right, ser_in : in std_logic;
ser_out : out std_logic
);
END ENTITY S_REG8;
ARCHITECTURE dflow OF S_REG8 IS
SIGNAL reg: std_logic_vector (7 downto 0);
SIGNAL selectors: std_logic_vector (1 downto 0);
BEGIN
selectors <= s_right & s_enable;
ser_out <= reg(7) when selectors = "01" else
reg(0);
shift_reg:
PROCESS (clk)
BEGIN
IF rising_edge (clk) THEN
IF selectors = "01" THEN
reg <= std_logic_vector(shift_left(unsigned(reg), 1));
reg (0) <= ser_in;
-- ser_out <= reg (7);
ELSIF selectors = "11" THEN
reg <= std_logic_vector(shift_right(unsigned(reg),1));
reg (7) <= ser_in;
-- ser_out <= reg (0);
END IF;
END IF;
END PROCESS;
END ARCHITECTURE;
For simulation I have been using Quartus II ModSim which I get the following results from:
The results look great. Adding a single 1 bit state into the register I can see it move to the left or right of the register depending on the toggling of inputs s_right or s_enable.
The use of the multiplexer on the set_out and reg(0) and (7) makes much more sense in comparison to the addition latch that I added to the original description.
MANY THANKS
How would anyone peform a rightshift or left shift in VHDL on a STD_LOGIC_VECTor...
It will not work , why??`
AN <= "0001";
CounterProcess: process(CLK,Switch)
begin
if rising_edge(CLK) then
if prescaler < limit then
prescaler <= prescaler + 1;
else
prescaler <= (others => '0');
counter <= counter + 1;
AN sll 1;
end if;
end if;
end process;
An <= anode;
Segment <= counter;
end Behavioral;
I get the Error message: sll can not have such operands in this context.
But in which context can it then be used in, and how can perform my left shift?
these are my includes:
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use ieee.std_logic_unsigned.all;
use ieee.numeric_std.all;
isn't the one needed to perform my leftshift operations included??
Complete code
entity Main is
PORT(
CLK: in std_logic;
LED: out std_logic_vector (7 downto 0);
Switch: in std_logic_vector(7 downto 0);
Segment: out std_logic_vector (7 downto 0);
AN: out std_logic_vector (3 downto 0)
);
end Main;
architecture Behavioral of Main is
signal counter: std_logic_vector (7 downto 0);
signal prescaler: std_logic_vector(25 downto 0);
signal limit: std_logic_vector (25 downto 0);
signal anode: std_logic_vector (3 downto 0);
begin
AN <= "0001";
ScalerChoice: Process(switch)
begin
CASE Switch IS
when "00000001" => limit <= "10111110101111000010000000"; -- 1 Hz;
when "00000010" => limit <= "00111111100101000000101011"; -- 3 HZ
When "00000100" => limit <= "00010011000100101101000000"; -- 10 Hz
when "00001000" => limit <= "00000111101000010010000000"; -- 25 Hz
When "00010000" => limit <= "00000011110100001001000000"; -- 50 Hz;
when "00100000" => limit <= "00000001111010000100100000"; -- 100 hz
when others => limit <= "00000000000000000000000001"; -- 50 MHz
end case;
end process;
CounterProcess: process(CLK,Switch)
begin
if rising_edge(CLK) then
if prescaler < limit then
prescaler <= prescaler + 1;
else
prescaler <= (others => '0');
counter <= counter + 1;
AN sll AN 1;
end if;
end if;
end process;
Segment <= counter;
end Behavioral;
In addition to what trumpetlicks said, use these packages instead. Make sure to enable the VHDL-2008 switch. Also try this with your FPGA vendor first as these require VHDL-2008 updates:
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use ieee.numeric_std.all;
use ieee.numeric_std_unsigned.all;
The above packages are all IEEE standards. The packages STD_LOGIC_ARITH and std_logic_unsigned are not IEEE standards. Note also that numeric_std and STD_LOGIC_ARITH conflict with each other and make it difficult (way beyond basic usage) to use the types signed and unsigned. Note that std_logic_unsigned conflicts with numeric_std_unsigned. So if your synthesis tool supports numeric_std_unsigned, I recommend using it instead. Furthermore, if it does not you should submit a bug report against it.
EDIT 1:
Your Code Edited with reset logic, notice the addition of the RESET signal to the ports list, the deletion of the asynchronous line setting that value, addition of RESET to the sensitivity list of your CounterProcess process, the addition of the if(RESET = '1') line, and change of your if to an elsif, as well as the change of your shifting line:
I actually don't know what your An <= Anode line is doing, and believe this to be in error also.
entity Main is PORT(
RESET: in std_logic;
CLK: in std_logic;
LED: out std_logic_vector(7 downto 0);
Switch: in std_logic_vector(7 downto 0);
Segment: out std_logic_vector(7 downto 0);
AN: out std_logic_vector(3 downto 0)
);
end Main;
architecture Behavioral of Main is
signal counter: std_logic_vector(7 downto 0);
signal prescaler: std_logic_vector(25 downto 0);
signal limit: std_logic_vector(25 downto 0);
signal anode: std_logic_vector(3 downto 0);
begin
ScalerChoice: Process(switch)
begin
CASE Switch IS
when "00000001" => limit <= "10111110101111000010000000"; -- 1 Hz;
when "00000010" => limit <= "00111111100101000000101011"; -- 3 HZ
When "00000100" => limit <= "00010011000100101101000000"; -- 10 Hz
when "00001000" => limit <= "00000111101000010010000000"; -- 25 Hz
When "00010000" => limit <= "00000011110100001001000000"; -- 50 Hz;
when "00100000" => limit <= "00000001111010000100100000"; -- 100 hz
when others => limit <= "00000000000000000000000001"; -- 50 MHz
end case;
end process;
CounterProcess: process(RESET, CLK, Switch)
begin
if(RESET = '1') then
AN <= "0001";
elsif rising_edge(CLK) then
if prescaler < limit then
prescaler <= prescaler + 1;
else
prescaler <= (others => '0');
counter <= counter + 1;
AN <= std_logic_vector(unsigned(AN) sll 1);
end if;
end if;
end process;
An <= anode;
Segment <= counter;
end Behavioral;
you need to write the line that you currently have:
AN sll 1;
as
AN <= AN sll 1;
Remember that AN is essentially like a variable that needs to be "set". Like your line above
counter <= counter + 1;
This code should be (and is) very simple, and I don't know what I am doing wrong.
Here is description of what it should do:
It should display a number on one 7-segment display. That number should be increased by one every time someone presses the push button. There is also reset button which sets the number to 0. That's it. Here is VHDL code:
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity PWM is
Port ( cp_in : in STD_LOGIC;
inc : in STD_LOGIC;
rst: in std_logic;
AN : out STD_LOGIC_VECTOR (3 downto 0);
segments : out STD_LOGIC_VECTOR (6 downto 0));
end PWM;
architecture Behavioral of PWM is
signal cp: std_logic;
signal CurrentPWMState: integer range 0 to 10;
signal inco: std_logic;
signal temp: std_logic_vector (3 downto 0);
begin
--cp = 100 Hz
counter: entity djelitelj generic map (CountTo => 250000) port map (cp_in, cp);
debounce: entity debounce port map (inc, cp, inco);
temp <= conv_std_logic_vector(CurrentPWMState, 4);
ss: entity decoder7seg port map (temp, segments);
process (inco, rst)
begin
if inco = '1' then
CurrentPWMState <= CurrentPWMState + 1;
elsif rst='1' then
CurrentPWMState <= 0;
end if;
end process;
AN <= "1110";
end Behavioral;
Entity djelitelj (the counter used to divide 50MHz clock):
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity PWM is
Port ( cp_in : in STD_LOGIC;
inc : in STD_LOGIC;
rst: in std_logic;
AN : out STD_LOGIC_VECTOR (3 downto 0);
segments : out STD_LOGIC_VECTOR (6 downto 0));
end PWM;
architecture Behavioral of PWM is
signal cp: std_logic;
signal CurrentPWMState: integer range 0 to 10;
signal inco: std_logic;
signal temp: std_logic_vector (3 downto 0);
begin
--cp = 100 Hz
counter: entity djelitelj generic map (CountTo => 250000) port map (cp_in, cp);
debounce: entity debounce port map (inc, cp, inco);
temp <= conv_std_logic_vector(CurrentPWMState, 4);
ss: entity decoder7seg port map (temp, segments);
process (inco, rst)
begin
if inco = '1' then
CurrentPWMState <= CurrentPWMState + 1;
elsif rst='1' then
CurrentPWMState <= 0;
end if;
end process;
AN <= "1110";
end Behavioral;
Debouncing entity:
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.STD_LOGIC_ARITH.all;
use IEEE.STD_LOGIC_UNSIGNED.all;
ENTITY debounce IS
PORT(pb, clock_100Hz : IN STD_LOGIC;
pb_debounced : OUT STD_LOGIC);
END debounce;
ARCHITECTURE a OF debounce IS
SIGNAL SHIFT_PB : STD_LOGIC_VECTOR(3 DOWNTO 0);
BEGIN
-- Debounce Button: Filters out mechanical switch bounce for around 40Ms.
-- Debounce clock should be approximately 10ms
process
begin
wait until (clock_100Hz'EVENT) AND (clock_100Hz = '1');
SHIFT_PB(2 Downto 0) <= SHIFT_PB(3 Downto 1);
SHIFT_PB(3) <= NOT PB;
If SHIFT_PB(3 Downto 0)="0000" THEN
PB_DEBOUNCED <= '1';
ELSE
PB_DEBOUNCED <= '0';
End if;
end process;
end a;
And here is BCD to 7-segment decoder:
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity decoder7seg is
port (
bcd: in std_logic_vector (3 downto 0);
segm: out std_logic_vector (6 downto 0));
end decoder7seg;
architecture Behavioral of decoder7seg is
begin
with bcd select
segm<= "0000001" when "0000", -- 0
"1001111" when "0001", -- 1
"0010010" when "0010", -- 2
"0000110" when "0011", -- 3
"1001100" when "0100", -- 4
"0100100" when "0101", -- 5
"0100000" when "0110", -- 6
"0001111" when "0111", -- 7
"0000000" when "1000", -- 8
"0000100" when "1001", -- 9
"1111110" when others; -- just - character
end Behavioral;
Does anyone see where I made my mistake(s) ?
I've tried that design on Spartan-3 Started board and it isn't working ... Every time I press the push button, I get crazy (random) values. The reset button is working properly.
Thanks !!!!
I guess the problem is here:
process (inco, rst)
begin
if inco = '1' then
CurrentPWMState <= CurrentPWMState + 1;
elsif rst='1' then
CurrentPWMState <= 0;
end if;
end process;
When rst='1' you will reset CurrentPWMState. But when inco='1' the you endlessly add 1 to CurrentPWMState. That's something like an asynchronous feedback loop through a latch. You should do something edge sensitive here. Probably you should capture inco using your clock signal, detect a 0->1 change and then add 1.
Agree with the previous answer.
A code like this should do the trick:
process (inco, ps, rst)
begin
if rst='1' then
CurrentPWMState <= '0';
prev_inco <= inco; -- This signal captures the previous value of inco
elsif ps'event and ps='1' then
if inco='1' and prev_inco='0' then -- Capture the flank rising.
CurrentPWMState <= CurrentPWMState + 1;
end if;
prev_inco <= inco;
end if;
end process;
I recognize I haven't tried the code (just coded in here) but I think it's ok.