getting error for VHDL shift_left operation - vhdl

I have been searching this for a while and have not been able to replicate any posted solutions online so I was hoping some of you wonderful people could help me out.
I am creating an ALU. i have a two 32 bit inputs and one 32 bit output along with a 5 bit shamt and a 4 bit control signal. My code is as follows with the error location commented on.
library ieee;
use ieee.std_logic_1164.all;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
use ieee.numeric_std.all;
Entity mips_alu IS
PORT(ALUControl : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
inputA, inputB : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
shamt : IN STD_LOGIC_VECTOR(4 DOWNTO 0);
Zero : OUT STD_LOGIC;
ALU_Result : OUT STD_LOGIC_VECTOR(31 DOWNTO 0)
);
END mips_alu;
ARCHITECTURE behavior of mips_alu IS
BEGIN
PROCESS(ALUControl)
BEGIN
CASE ALUControl is
WHEN "0000" =>
ALU_Result <= inputA AND inputB;
WHEN "0001" =>
ALU_Result <= inputA OR inputB;
WHEN "0010" =>
ALU_Result <= inputA + inputB;
WHEN "0110" =>
ALU_Result <= inputA - inputB;
WHEN "0111" =>
IF (inputA < inputB) THEN
ALU_Result <= inputA;
END IF;
WHEN "1000" =>
ALU_Result <= shift_left(inputB, to_integer(unsigned(shamt)));
-- The line above is where i get my first error, The following lines will have the same issue
WHEN "1001" =>
ALU_Result <= shift_right(inputB, shamt);
WHEN "1010" =>
ALU_Result <= shift_left(inputB, inputA);
WHEN "1011" =>
ALU_Result <= shift_right(inputB, inputA);
WHEN "1100" =>
ALU_Result <= inputA NOR inputB;
WHEN "1101" =>
ALU_Result <= inputB(31 DOWNTO 16);
WHEN OTHERS =>
ALU_Result <= inputA;
END CASE;
END PROCESS;
END behavior;
The error I am getting says:
10511 VHDL Qualified Expression error at mips_alu.vhd(33): shift_left type specified in qualified expression must match std_logic_vector type that is implied for expression by context
I have tried several variations of this so if i am missing something please let me know, all help is appreciated as I am a bit of a novice to vhdl

In the numeric_std document you can find the function shift_left or shift_right. In both descriptions there you can see that function SHIFT_LEFT (ARG: UNSIGNED; COUNT: NATURAL) return UNSIGNED;. So you need to use casting of your std_logic_vector to unsigned.
In your case it will looks like:
ALU_Result <= std_logic_vector(shift_left(unsigned(inputB), to_integer(unsigned(shamt))));
end etc. for other lines where you use shift_left or shift_right function.

What I usually do is just this:
ALU_Result <= inputB(30 downto 0) & '0';
This stores is ALU_Result a vector equal to InputB shifted once.
In case you want to shift it more times you can use a loop.
while (i<to_integer(unsigned(shamt))) loop
ALU_Result <= inputB(30 downto 0) & '0';
i:=i+1;
end loop;
Its not an elegant solution but it will probably work.
For shifting to the right do:
ALU_Result <= '0' & inputB(31 downto 1);

Related

Carry/Borrow in VHDL ALU

I am making a generic N-bit ALU in VHDL. I am having trouble assigning the value for the carry for addition, or borrow for subtraction. I have tried the following:
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
entity alu is
generic(n: integer :=1); --Default to 1
port (
a : in std_logic_vector(n-1 downto 0);
b : in std_logic_vector(n-1 downto 0);
op : in std_logic_vector(1 downto 0);
output : out std_logic_vector(n-1 downto 0);
carryborrow: out std_logic
);
end alu;
architecture Behavioral of alu is
signal result: std_logic_vector(n downto 0);
begin
process( a, b, op )
begin
case op is
when "00" =>
result(n) <= '0';
result(n-1 downto 0) <= a and b; --and gate
output <= result(n-1 downto 0);
carryborrow <= '0';
when "01" =>
result(n) <= '0';
result(n-1 downto 0) <= a or b; --or gate
output <= result(n-1 downto 0);
carryborrow <= '0';
when "10" =>
result(n) <= '0';
result(n-1 downto 0) <= std_logic_vector(signed(a) + signed(b)); --addition
output <= result(n-1 downto 0);
carryborrow <= result(n);
when "11" =>
result(n) <= '0';
result(n-1 downto 0) <= std_logic_vector(signed(a) - signed(b)); --subtraction
output <= result(n-1 downto 0);
carryborrow <= result(n);
when others =>
NULL;
end case;
end process;
end Behavioral;
This seems to set the carryborrow bit to always be 0. How can I assign it to what it should be without type errors?
There are bugs in your code:
i) You have not taken into account the fact that signals are not updated immediately. Consequently, the following lines will not do as I think you are expecting:
result(n) <= '0';
result(n-1 downto 0) <= a and b; --and gate
output <= result(n-1 downto 0);
Instead, you need to take the lines driving output and carryborrow outside the combinational process, as you can see below.
ii) Assuming you wish this code to be synthesisable, simply putting NULL in your always branch will result in latches being inferred. You need to drive result in the others branch, too.
So, making an assumption about how your carry output is to behave with the and and or operations, this is how I would have written your code:
architecture Behavioral of alu is
signal result: std_logic_vector(n downto 0);
begin
process( a, b, op )
begin
case op is
when "00" =>
result <= '0' & (a and b); --and gate
when "01" =>
result <= '0' & (a or b); --or gate
when "10" =>
result <= std_logic_vector(resize(signed(a), n+1) + resize(signed(b), n+1)); --addition
when "11" =>
result <= std_logic_vector(resize(signed(a), n+1) - resize(signed(b), n+1)); --subtraction
when others =>
result <= (others => 'X');
end case;
end process;
output <= result(n-1 downto 0);
carryborrow <= result(n);
end Behavioral;
I normally do this:
result <= std_logic_vector(signed(a(n-1) & a) + signed(b(n-1) & b));
result <= std_logic_vector(signed(a(n-1) & a) - signed(b(n-1) & b));
Sign extend and then do the operation to take care of overflow, when the result is one extra bit long.
Hmm, consider this in a 4 bit environment, say a="0101" and b="1001". Adding them shall give the output="1110", with NO carry.
However, sign extending with resize(signed(a), n+1) and resize(signed(b), n+1) will set a="00101" and b="11001" and hence result="11110" and carryborrow='1', which is wrong!
By sign extending vectors a and b, the numeral range has increased to 5 bits, and thus result needs to be 6 bits to be able to hold carry, and we're back to square one.
Vectors a and b should only be zero extended, that is '0' & a and '0' & b before adding them to result, and then carryborrow, as MSB(Most Significant Bit) of result, will get the correct value.

Error: /..integrator.vhd(47): near "process": (vcom-1576) expecting IF VHDL

I'm trying to add two registers storing signed bits one of 3-bit[FRQ(2 downto 0)] and other is 7-bit[PHS(6 downto 0)]...and has to store the addition of these two registers in 7-bit register [PHS(6 downto 0)]. Thanks in advance for your helpful gesture.
the error I get is..>>>
Error: /..integrator.vhd(47): near "process": (vcom-1576) expecting IF VHDL
here is my code:
library IEEE;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
--use ieee.std_logic_unsigned.all;
entity integ is
port (
SMP_CLK : in std_logic;
RESET : in std_logic;
PHS : out signed (6 downto 0);
FRQ : in signed (2 downto 0)
);
end integ;
architecture behaviour of integ is
signal sig_FRQ : signed(2 downto 0) := (others => '0');
signal ext_FRQ : signed(6 downto 0) := (others => '0');
signal sig_PHS : signed(6 downto 0) := (others => '0');
signal temp_PHS : signed(6 downto 0) := (others => '0');
begin
sig_FRQ <=FRQ;
temp_PHS <= sig_PHS;
--PHS <=signal_PHS;
process (SMP_CLK, RESET)
begin
if sig_FRQ(2)='1' then
ext_FRQ(6 downto 3) <= b"0000";
else
ext_FRQ(6 downto 3) <= b"1111";
--end if;
if RESET='1' then
sig_PHS <= b"0000000";
elsif (rising_edge(SMP_CLK) ) then
-- temp_PHS <= sig_PHS;
sig_PHS <= signed(ext_FRQ) + signed(temp_PHS);
end process;
sig_PHS => PHS;
end behaviour;
You have some mess with if-elsif-else statement. After the line with ext_FRQ(6 downto 3) <= b"1111"; you have commented --end if; if you want to continue if-elsif-else statement next condition should start with elsif word rather than simple if as in your code.
And you need to close the if-elsif-else construction in the end.
As well as you need to add to sensitivity list sig_FRQ signal because you use it in comparison, if you don't add it to sensitivity list the following construction
if sig_FRQ(2)='1' then
ext_FRQ(6 downto 3) <= b"0000";
else
ext_FRQ(6 downto 3) <= b"1111";
end if;
will work wrong.
In your case I suppose right version of the if-elsif-else constructions looks like:
process (sig_FRQ)
begin
if sig_FRQ(2)='1' then
ext_FRQ(6 downto 3) <= b"0000";
else
ext_FRQ(6 downto 3) <= b"1111";
end if;
end process;
process (SMP_CLK, RESET)
if RESET='1' then
sig_PHS <= b"0000000";
elsif (rising_edge(SMP_CLK)) then
--temp_PHS <= sig_PHS;
sig_PHS <= ext_FRQ + temp_PHS;
end if;
end process;
In the end, if you would like to assign result to output, you need to use another operator
PHS <= sig_PHS;.

Concurrent Statement on a case VHDL

Hi all i'm trying to synthesize a VHDL code using alliance tool. But im having an illegal concurrent statement error. I'm new in VHDL and i'm trying to understand the concurrent and sequential statements, So i dont really understand why i'm getting a illegal concurrent statement inside a the case. Could you please help me on this error.
Here is a piece of the code, but is basically the same:
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity reg_P is
port (
A : in unsigned(7 downto 0);
CLK : in std_logic;
EstPresente : in unsigned(7 downto 0);
P : out unsigned(7 downto 0);
RI : in unsigned(7 downto 0);
RPS : in std_logic
);
end reg_P;
architecture FromVerilog of reg_P is
signal P_Reg : unsigned(7 downto 0);
begin
P <= P_Reg;
process (CLK)
begin
if (rising_edge(CLK)) then
if ((not RPS) = '1') then
P_Reg <= X"00";
else
case EstPresente is
when X"02" then
case RI is
when X"16" then
P_Reg <= A;
when X"36" then
P_Reg <= (P_Reg - X"01");
when X"26" then
P_Reg <= (P_Reg - X"01");
when others then
P_Reg <= P_Reg;
end case;
when others then
P_Reg <= P_Reg;
end case;
end if;
end if;
end process;
end architecture;
The thens in your case statement choices should be the compound delimiter =>.
Replace those 6 instances and your code analyzes.
case EstePresente is
when X"02" =>
case RI is
when X"16" =>
P_Reg <= A;
when X"36" =>
P_Reg <= (P_Reg - X"01");
when X"26" =>
P_Reg <= (P_Reg - X"01");
when others =>
P_Reg <= P_Reg;
end case;
when others =>
P_Reg <= P_Reg;
end case;
ghdl -a reg_p.vhdl
reg_p.vhdl:26:19: '=>' is expected instead of 'then'
ghdl: compilation error
From a historical perspective synthesis was so costly you were expected to validate your models through simulation before synthesis.
Simulation tools tend to have better error reporting.

4bit ALU VHDL code

I am writing a code for a 4 bit ALU and I have a problem when I want to write for shift left operation. I have two inputs (operandA and operandB ). I want to convert the operandB into decimal (for example "0010" into '2') and then shift operandA 2 times to the left. my code is compiled but I am not sure that it is true. Thank you in advance.
entity ALU is
port(
reset_n : in std_logic;
clk : in std_logic;
OperandA : in std_logic_vector(3 downto 0);
OperandB : in std_logic_vector(3 downto 0);
Operation : in std_logic_vector(2 downto 0);
Start : in std_logic;
Result_Low : out std_logic_vector(3 downto 0);
Result_High : out std_logic_vector(3 downto 0);
Ready : out std_logic;
Errorsig : out std_logic);
end ALU;
architecture behavior of ALU is
signal loop_nr : integer range 0 to 15;
begin
process (reset_n, clk, operation)
variable tempHigh : std_logic_vector(4 downto 0);
begin
if (reset_n = '0') then
Result_Low <= (others => '0');
Result_High <= (others => '0');
Errorsig <= '0';
elsif (clk'event and clk = '1') then
case operation is
when "001" =>
for i in 0 to loop_nr loop
loop_nr <= to_integer(unsigned(OperandB));
Result_Low <= OperandA(2 downto 0)&'0';
Result_High <= tempHigh(2 downto 0) & OperandA(3);
end loop;
Ready <= '1';
Errorsig <= '0';
when "010" =>
Result_Low <= OperandB(0)& OperandA(3 downto 1);
Result_High <= OperandB(3 downto 1);
Ready <= '1';
when others =>
Result_Low <= (others => '0');
ready <= '0';
Errorsig <= '0';
end case;
end if;
end process;
end behavior;
For shifting left twice the syntax should be the following:
A <= A sll 2; -- left shift logical 2 bits
I don't quite understand why is it required to convert operand B in decimal. It can be used as a binary or decimal value or for that matter hexadecimal value at any point of time irrelevant of the base it was saved in.
The operator sll may not always work as expected before VHDL-2008 (read more
here),
so consider instead using functions from ieee.numeric_std for shifting, like:
y <= std_logic_vector(shift_left(unsigned(OperandA), to_integer(unsigned(OperandB))));
Note also that Result_High is declared in port as std_logic_vector(3 downto
0), but is assigned in line 41 as Result_High <= OperandB(3 downto 1), with
assign having one bit less than size.
Assumption for code is that ieee.numeric_std is used.
The reason you've been urged to use the likes of sll is because in general
synthesis tools don't support loop statements with non-static bounds
(loop_nr). Loops are unfolded which requires a static value to determine how
many loop iterations are unfolded (how much hardware to generate).
As Morten points out your code doesn't analyze, contrary to you assertion
that it compiles.
After inserting the following four lines at the beginning of your code we see
an error at line 41:
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
--(blank, a spacer that doesn't show up in the code highlighter)
ghdl -a ALU.vhdl
ALU.vhdl:41:26: length of value does not match length of target
ghdl: compilation error
Which looks like
Result_High <= '0' & OperandB(3 downto 1);
was intended in the case statement, choice "010" (an srl equivalent hard
coded to a distance of 1, presumably to match the correct behavior of the sll
equivalent). After which your design description analyzes.
Further there are other algorithm description errors not reflected in VHDL
syntax or semantic errors.
Writing a simple test bench:
library ieee;
use ieee.std_logic_1164.all;
entity alu_tb is
end entity;
architecture foo of alu_tb is
signal reset_n: std_logic := '0';
signal clk: std_logic := '0';
signal OperandA: std_logic_vector(3 downto 0) :="1100"; -- X"C"
signal OperandB: std_logic_vector(3 downto 0) :="0010"; -- 2
signal Operation: std_logic_vector(2 downto 0):= "001"; -- shft right
signal Start: std_logic; -- Not currently used
signal Result_Low: std_logic_vector(3 downto 0);
signal Result_High: std_logic_vector(3 downto 0);
signal Ready: std_logic;
signal Errorsig: std_logic;
begin
DUT:
entity work.ALU
port map (
reset_n => reset_n,
clk => clk,
OperandA => OperandA,
OperandB => OperandB,
Operation => Operation,
Start => Start,
Result_Low => Result_Low,
Result_High => Result_High,
Ready => Ready,
Errorsig => Errorsig
);
CLOCK:
process
begin
wait for 10 ns;
clk <= not clk;
if Now > 100 ns then
wait;
end if;
end process;
STIMULUS:
process
begin
wait for 20 ns;
reset_n <= '1';
wait;
end process;
end architecture;
Gives us a demonstration:
The first thing that sticks out is that Result_High gets some 'U's. This is
caused by tempHigh not being initialized or assigned.
The next thing to notice is that the shift result is wrong (both Result_Low
and Result_High). I'd expect you'd want a "0011" in Result_High and "0000" in
Result_Low.
You see the result of exactly one left shift - ('U','U','U','1') in
Result_High and "1000" in Result_Low.
This is caused by executing a loop statement in delta cycles (no intervening
simulation time passage). In a process statement there is only one driver for
each signal. The net effect of that is that there is only one future value
for the current simulation time and the last value assigned is going to be
the one that is scheduled in the projected output waveform for the current
simulation time. (Essentially, the assignment in the loop statement to a
signal occurs once, and because successive values depend on assignment
occurring it looks like there was only one assignment).
There are two ways to fix this behavior. The first is to use variables
assigned inside the loop and assign the corresponding signals to the
variables following the loop statement. As noted before the loop bound isn't
static and you can't synthesis the loop.
The second way is to eliminate the loop by executing the shift assignments
sequentially. Essentially 1 shift per clock, signaling Ready after the last
shift occurs.
There's also away to side step the static bounds issue for loops by using a
case statement (or in VHDL 2008 using a sequential conditional signal
assignment of sequential selected signal assignment should your synthesis
tool vendor support them). This has the advantage of operating in one clock.
Note all of these require having an integer variable holding
to_integer(unsigned(OperandB)).
And all of this can be side stepped when your synthesis tool vendor supports
sll (and srl for the other case) or SHIFT_LEFT and SHIFT_RIGHT from package
numeric_std, and you are allowed to use them.
A universal (pre VHDL 2008) fix without using sll or SHIFT_LEFT might be:
begin
process (reset_n, clk, operation)
variable tempHigh : std_logic_vector(4 downto 0);
variable loop_int: integer range 0 to 15;
begin
if (reset_n = '0') then
Result_Low <= (others => '0');
Result_High <= (others => '0');
Errorsig <= '0';
elsif (clk'event and clk = '1') then
case operation is
when "001" =>
loop_int := to_integer(unsigned(OperandB));
case loop_int is
when 0 =>
Result_Low <= OperandA;
Result_High <= (others => '0');
when 1 =>
Result_Low <= OperandA(2 downto 0) & '0';
Result_High <= "000" & OperandA(3);
when 2 =>
Result_Low <= OperandA(1 downto 0) & "00";
Result_High <= "00" & OperandA(3 downto 2);
when 3 =>
Result_Low <= OperandA(0) & "000";
Result_High <= "0" & OperandA(3 downto 1);
when 4 =>
Result_Low <= (others => '0');
Result_High <= OperandA(3 downto 0);
when 5 =>
Result_Low <= (others => '0');
Result_High <= OperandA(2 downto 0) & '0';
when 6 =>
Result_Low <= (others => '0');
Result_High <= OperandA(1 downto 0) & "00";
when 7 =>
Result_Low <= (others => '0');
Result_High <= OperandA(0) & "000";
when others =>
Result_Low <= (others => '0');
Result_High <= (others => '0');
end case;
-- for i in 0 to loop_nr loop
-- loop_nr <= to_integer(unsigned(OperandB));
-- Result_Low <= OperandA(2 downto 0)&'0';
-- Result_High <= tempHigh(2 downto 0) & OperandA(3);
-- end loop;
Ready <= '1';
Errorsig <= '0';
Which gives:
The right answer (all without using signal loop_nr).
Note that all the choices in the case statement aren't covered by the simple
test bench.
And of course like most things there's more than two ways to get the desired
result.
You could use successive 2 to 1 multiplexers for both Result_High and
Result_Low, with each stage fed from the output of the previous stage (or
OperandA for the first stage) as the A input the select being the appropriate
'bit' from OperandB, and the B input to the multiplexers the previous stage
output shifted by 1 logically ('0' filled).
The multiplexers can be functions, components or procedure statements. By
using a three to one multiplexer you can implement both symmetrical shift
Operation specified operations (left and right). Should you want to include signed shifts,
instead of '0' filled right shifts you can fill with the sign bit value. ...
You should also be assigning Ready <= '0' for those cases where valid
successive Operation values can be dispatched.
And because your comment on one of the answers requires the use of a loop with an integer value:
process (reset_n, clk, operation)
variable tempHigh : std_logic_vector(4 downto 0);
variable tempLow: std_logic_vector(3 downto 0); --added
variable loop_int: integer range 0 to 15; --added
begin
if (reset_n = '0') then
Result_Low <= (others => '0');
Result_High <= (others => '0');
Errorsig <= '0';
elsif (clk'event and clk = '1') then
case operation is
when "001" =>
tempLow := OperandA; --added
tempHigh := (others => '0'); --added
loop_int := to_integer(unsigned(OperandB)); --added
-- for i in 0 to loop_nr loop
-- loop_nr <= to_integer(unsigned(OperandB));
-- Result_Low <= OperandA(2 downto 0)&'0';
-- Result_High <= tempHigh(2 downto 0) & OperandA(3);
-- end loop;
-- More added:
if loop_int /= 0 then
for i in 1 to loop_int loop
tempHigh (3 downto 0) := tempHigh (2 downto 0) & tempLow(3);
-- 'read' tempLow(3) before it's updated
tempLow := tempLow(2 downto 0) & '0';
end loop;
Result_Low <= tempLow;
Result_High <= tempHigh(3 downto 0);
else
Result_Low <= OperandA;
Result_High <= (others => '0');
end if;
Ready <= '1';
Errorsig <= '0';
Which gives:
And to demonstrate both halves of Result are working OperandA's default value has been changed to "0110":
Also notice the loop starts at 1 instead of 0 to prevent you from having an extra shift and there's a check for non-zero loop_int to prevent the for loop from executing at least once.
And is it possible to make a synthesizable loop in these circumstances?
Yes.
The loop has to address all possible shifts (the range of loop_int) and test whether or not i falls under the shift threshold:
process (reset_n, clk, operation)
variable tempHigh : std_logic_vector(4 downto 0);
variable tempLow: std_logic_vector(3 downto 0); --added
subtype loop_range is integer range 0 to 15;
variable loop_int: integer range 0 to 15; --added
begin
if (reset_n = '0') then
Result_Low <= (others => '0');
Result_High <= (others => '0');
Errorsig <= '0';
elsif (clk'event and clk = '1') then
case operation is
when "001" =>
tempLow := OperandA; --added
tempHigh := (others => '0'); --added
loop_int := to_integer(unsigned(OperandB)); --added
for i in loop_range loop
if i < loop_int then
tempHigh (3 downto 0) := tempHigh (2 downto 0) & tempLow(3);
-- 'read' tempLow(3) before it's updated
tempLow := tempLow(2 downto 0) & '0';
end if;
end loop;
Result_Low <= tempLow;
Result_High <= tempHigh(3 downto 0);

How to add std_logic to an integer value

I am trying to run two 7 segments here, I have searched everywhere but could not find a satisfactory reply, how can I add 1 to a std_logic ? I tried the logic_arith library as well but nothing works. I read somewhere that i gotta use a (0 to 0) vector but umm i didn't really get that part. Here is my code
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
use ieee.std_logic_arith.all;
entity blah is
Port ( clk : in STD_LOGIC;
anode: out STD_LOGIC_VECTOR (3 downto 0);
segment: out STD_LOGIC_VECTOR (6 downto 0));
end blah;
architecture Behavioral of blah is
signal sel: STD_LOGIC;
signal r_anode: STD_LOGIC_VECTOR (3 downto 0);
begin
anode <= r_anode;
process (clk) begin
if (clk'event and clk = '1') then
sel <= sel+1;
end if;
end process;
process (sel) begin
case sel is
when '0' => r_anode <= "1110";
when '1' => r_anode <= "1101";
when others => r_anode <= "1111";
end case;
case r_anode is
when "1110" => segment <= "0100100";
when "1101" => segment <= "0010010";
when others => segment <= "1111111";
end case;
end process;
end;
And the error
ERROR:HDLParsers:808 - "E:/Xilinx Projects/blah/blah.vhd" Line 19. + can not have such operands in this context.
The sel is only a single bit, so adding 1 is like a not sel.
However, if sel is more bits in a std_logic_vector, you can add a
natural to std_logic_vector as unsigned with:
sel <= std_logic_vector(unsigned(sel) + 1);
Use only ieee.numeric_std, thus remove the ieee.std_logic_arith, since
std_logic_arith is not a standard library (Synopsys proprietary).

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