When compiling my testbench I get the following error:
"Unknown formal identifier "_"". This happens for every input of the entity I'm testing.
Here is my code:
entity Scoreboard is
port( BTN: in std_logic_vector(3 downto 0);
SWITCHES: in std_logic_vector(17 downto 0);
CLK_50 : in std_logic;
maxreset: in std_logic;
Display0: out std_logic_vector(6 downto 0);
Display1: out std_logic_vector(6 downto 0);
Display2: out std_logic_vector(6 downto 0);
Display3: out std_logic_vector(6 downto 0);
Display4: out std_logic_vector(6 downto 0);
Display5: out std_logic_vector(6 downto 0);
Display6: out std_logic_vector(6 downto 0);
Display7: out std_logic_vector(6 downto 0);
GREEN: out std_logic_vector(7 downto 0);
RED: out std_logic_vector(17 downto 0));
end Scoreboard;
And my test bench:
entity Scoreboard is
end Scoreboard;
architecture Stimulus of Scoreboard is
-- Sinais para ligar as entradas da uut
signal s_BTN: std_logic_vector(3 downto 0);
signal s_SWITCHES: std_logic_vector(17 downto 0);
signal s_CLK_50, s_maxreset: std_logic;
-- Sinal para ligar as saidas da uut
signal s_Display0, s_Display1, s_Display2, s_Display3, s_Display4, s_Display5, s_Display6, s_Display7: std_logic_vector(6 downto 0);
signal s_GREEN: std_logic_vector(7 downto 0);
signal s_RED: std_logic_vector(17 downto 0);
-- Outros
-- Outros
constant clk_period: time := 20 ns; -- 50MHz
begin
-- Instanciação da UUT --
uut: entity work.Scoreboard(Shell)
port map(BTN => s_BTN,
SWITCHES => s_SWITCHES,
CLK_50 => s_CLK_50,
maxreset => s_maxreset,
Display0 => s_Display0,
Display1 => s_Display1,
Display2 => s_Display2,
Display3 => s_Display3,
Display4 => s_Display4,
Display5 => s_Display5,
Display6 => s_Display6,
Display7 => s_Display7,
GREEN => s_GREEN,
RED => s_RED);
The entity "Scoreboard" is not the top level entity but has many entities under it.
You have two entities with the name Scoreboard. The second one you refer to as your test bench has no port interface list. As soon as the entity declaration:
entity Scoreboard is
end Scoreboard;
is analyzed you no longer have a port interface declaration to reference in a direct entity instantiation statement.
Change the name of your test bench entity (e.g. Scoreboard_tb). Also in the architecture declaration.
Related
The following code contains a vhdl file and a test bench for it.
Main file
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity lici is
port(PT_MSB : in std_logic_vector(31 downto 0);
PT_LSB: in std_logic_vector( 31 downto 0);
--key: in std_logic_vector(127 downto 0);
RK1: in std_logic_vector(31 downto 0);
RK2: in std_logic_vector(31 downto 0);
clk: in std_logic;
CT_LSB: out std_logic_vector(31 downto 0);
CT_MSB: out std_logic_vector(31 downto 0);
check: out std_logic_vector(31 downto 0)
);
end lici;
architecture beh of lici is
type S_BOX is array(15 downto 0)of std_logic_vector(3 downto 0);
signal sub: S_BOX:=(0=>x"3",1=>x"F",2=>x"E",3=>x"1",4=>x"0",5=>x"A",6=>x"5",7=>x"8",8=>x"c",9=>x"4",10=>x"B",11=>x"2",12=>x"9",13=>x"7",14=>x"6",15=>x"D");
begin
process(clk)
Variable var_PT_MSB : std_logic_vector(31 downto 0);
variable var_PT_LSB : std_logic_vector( 31 downto 0);
variable var_EN_PT_MSB: std_logic_vector(31 downto 0);
variable var_XOR_RK_SHR7: std_logic_vector(31 downto 0);
variable var_XOR_SHL3: std_logic_vector(31 downto 0);
variable var_CT_LSB: std_logic_vector(31 downto 0);
variable S_data: std_logic_vector(3 downto 0);
variable outside_counter: natural:= 0;
variable i: natural:= 1;
begin
var_PT_MSB:= PT_MSB;
var_PT_LSB:= PT_LSB;
if(outside_counter< 31) then
if(clk'event and clk='1' and i <= 8) then
S_data:= (var_PT_MSB(31 downto 28) and x"F");
case S_data is
when x"0"=> var_EN_PT_MSB(35-(i*4) downto 32-(i*4)):=sub(0);
when x"1"=> var_EN_PT_MSB(35-(i*4) downto 32-(i*4)):=sub(1);
when x"2"=> var_EN_PT_MSB(35-(i*4) downto 32-(i*4)):=sub(2);
when x"3"=> var_EN_PT_MSB(35-(i*4) downto 32-(i*4)):=sub(3);
when x"4"=> var_EN_PT_MSB(35-(i*4) downto 32-(i*4)):=sub(4);
when x"5"=> var_EN_PT_MSB(35-(i*4) downto 32-(i*4)):=sub(5);
when x"6"=> var_EN_PT_MSB(35-(i*4) downto 32-(i*4)):=sub(6);
when x"7"=> var_EN_PT_MSB(35-(i*4) downto 32-(i*4)):=sub(7);
when x"8"=> var_EN_PT_MSB(35-(i*4) downto 32-(i*4)):=sub(8);
when x"9"=> var_EN_PT_MSB(35-(i*4) downto 32-(i*4)):=sub(9);
when x"A"=> var_EN_PT_MSB(35-(i*4) downto 32-(i*4)):=sub(10);
when x"B"=> var_EN_PT_MSB(35-(i*4) downto 32-(i*4)):=sub(11);
when x"C"=> var_EN_PT_MSB(35-(i*4) downto 32-(i*4)):=sub(12);
when x"D"=> var_EN_PT_MSB(35-(i*4) downto 32-(i*4)):=sub(13);
when x"E"=> var_EN_PT_MSB(35-(i*4) downto 32-(i*4)):=sub(14);
when others=>var_EN_PT_MSB(35-(i*4) downto 32-(i*4)):=sub(15);
end case;
var_PT_MSB:= std_logic_vector(shift_left(unsigned(var_PT_MSB),4));
i:=i+1;
end if;
var_XOR_SHL3:= var_EN_PT_MSB xor RK1 xor var_PT_LSB;
var_XOR_SHL3:= std_logic_vector(rotate_left(unsigned(var_XOR_SHL3),3));
var_XOR_RK_SHR7:= var_EN_PT_MSB xor RK2 xor var_XOR_SHL3;
CT_LSB<= std_logic_vector(rotate_right(unsigned(var_XOR_RK_SHR7),7));
var_CT_LSB:= std_logic_vector(rotate_right(unsigned(var_XOR_RK_SHR7),7));
CT_MSB<= var_XOR_SHL3;
var_PT_MSB:= var_XOR_SHL3;
var_PT_LSB:= var_CT_LSB;
check<= var_EN_PT_MSB;
outside_counter:= outside_counter+1;
end if;
end process;
end beh;
--------------------------------------------------------------------------
This is the test bench for it
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity lici_tb is
end lici_tb;
architecture behav of lici_tb is
component lici is
port(PT_MSB : in std_logic_vector(31 downto 0);
PT_LSB: in std_logic_vector( 31 downto 0);
RK1: in std_logic_vector(31 downto 0);
RK2: in std_logic_vector(31 downto 0);
clk: in std_logic;
CT_LSB: out std_logic_vector (31 downto 0);
CT_MSB: out std_logic_vector(31 downto 0);
check: out std_logic_vector(31 downto 0)
);
end component;
signal clk :std_logic := '0';
signal PT_MSB:std_logic_vector(31 downto 0):=x"ABCDEF01";
signal PT_LSB:std_logic_vector( 31 downto 0):=x"23456789";
signal RK1:std_logic_vector(31 downto 0):=x"00000010";
signal RK2:std_logic_vector(31 downto 0):= x"00000001";
signal CT_LSB:std_logic_vector(31 downto 0);
signal CT_MSB: std_logic_vector(31 downto 0);
signal check: std_logic_vector(31 downto 0);
constant CLK_PERIOD : time := 10 ns;
begin
uut : lici port map (
PT_MSB => PT_MSB,
PT_LSB=>PT_LSB,
RK1=>RK1,
RK2=> RK2,
clk => clk,
CT_LSB=>CT_LSB,
CT_MSB => CT_MSB,
check=>check
);
Clk_process :process
begin
clk <= '0';
wait for CLK_PERIOD/2; --for half of clock period clk stays at '0'.
clk <= '1';
wait for CLK_PERIOD/2; --for next half of clock period clk stays at '1'.
end process;
end;
At the end I need to have 31 values in CT_LSB and CT_MSB.
In each cycle I wish to have different encrypted values in CT_LSB and CT_MSB,
In one cycle one iteration of outside_counter needs to happen in which 8 NIBBLE has to encrypted.
This entire code needs to work without using a For Loops.
Can someone help me with this?
I'm trying to simulate a VHDL project but modelsim gives me the following error message:
Error: (vsim-3173) Entity 'C:/Users/chose/Documents/CTD/teste/SELETORES/simulation/modelsim/rtl_work.seletores' has no architecture.
I tryed creatindg another project and it gives me the same error. I was able to sim other projects before, doing the same thing.
I'm running Quartus Prime Lite Edition 16.0 and Modelsim 10.5b. The code i'm trying to simulate is:
library IEEE;
use IEEE.Std_Logic_1164.all;
entity SELETORES is
port( IN_POT: in std_logic;
OUT_POT, REG_ALARM, REG_OPEN, CONTA, SW
: in std_logic_vector(9 downto 0);
MODE : in std_logic_vector(39 downto 0);
SEL_DISP, SEL_LED
: in std_logic_vector(1 downto 0);
LED_OUT, SEL_TIME, SEL_POT
: out std_logic_vector(9 downto 0);
REG : out std_logic_vector(19 downto 0)
);
end SELETORES;
architecture SELETORES_bhv of SELETORES is
signal decod_mux : std_logic_vector(19 downto 0);
component mux_4x1_20
port (W,X,Y,Z: in std_logic_vector(19 downto 0);
S: in std_logic_vector(1 downto 0);
F: out std_logic_vector(19 downto 0)
);
end component;
component mux_4x1_10
port (W,X,Y,Z: in std_logic_vector(9 downto 0);
S: in std_logic_vector(1 downto 0);
F: out std_logic_vector(9 downto 0)
);
end component;
component mux_2x1
port (W,X: in std_logic_vector(9 downto 0);
S: in std_logic;
F: out std_logic_vector(9 downto 0)
);
end component;
component decod_time
port( ENTRADA : in std_logic_vector(9 downto 0);
SAIDA: out std_logic_vector(19 downto 0)
);
end component;
begin
L1 : mux_4x1_10 port map ("0000000000", REG_OPEN, OUT_POT, REG_ALARM, SEL_LED, LED_OUT);
L2 : mux_2x1 port map (SW, MODE(19 downto 10), SEL_DISP(0) and not(SEL_DISP(1)), SEL_TIME);
L3 : decod_time port map (CONTA, decod_mux);
L4 : mux_4x1_20 port map ("00000110010111101111", MODE(39 downto 20), decod_mux, "11111100011100111101", SEL_DISP, REG);
L5 : mux_2x1 port map (SW, MODE(9 downto 0), IN_POT, SEL_POT);
end SELETORES_bhv;
First of all you have some syntax errors in your L2 component instantiation. Secondly, in my opinion this is the right way to do it (operators are not permitted in port maps):
library IEEE;
use IEEE.std_logic_1164.all;
entity SELETORES is
port( IN_POT: in std_logic;
OUT_POT, REG_ALARM, REG_OPEN, CONTA, SW
: in std_logic_vector(9 downto 0);
MODE : in std_logic_vector(39 downto 0);
SEL_DISP, SEL_LED
: in std_logic_vector(1 downto 0);
LED_OUT, SEL_TIME, SEL_POT
: out std_logic_vector(9 downto 0);
REG : out std_logic_vector(19 downto 0)
);
end SELETORES;
architecture SELETORES_bhv of SELETORES is
-- Component declarations
component mux_4x1_20
port (W,X,Y,Z: in std_logic_vector(19 downto 0);
S1: in std_logic_vector(1 downto 0);
F: out std_logic_vector(19 downto 0)
);
end component;
component mux_4x1_10
port (W,X,Y,Z: in std_logic_vector(9 downto 0);
S2: in std_logic_vector(1 downto 0);
F: out std_logic_vector(9 downto 0)
);
end component;
component mux_2x1
port (W,X: in std_logic_vector(9 downto 0);
S3: in std_logic;
F: out std_logic_vector(9 downto 0)
);
end component;
component decod_time
port(ENTRADA : in std_logic_vector(9 downto 0);
SAIDA: out std_logic_vector(19 downto 0)
);
end component;
--End component declarations
-- Internal signals
signal decod_mux : std_logic_vector(19 downto 0);
signal foobar: std_logic;
--End Internal Signals
begin
foobar <= SEL_DISP(0) AND NOT SEL_DISP(1);
L1 : mux_4x1_10 port map ("0000000000", REG_OPEN, OUT_POT, REG_ALARM, SEL_LED, LED_OUT);
L2 : mux_2x1 port map (SW, MODE(19 downto 10), foobar, SEL_TIME);
L3 : decod_time port map (CONTA, decod_mux);
L4 : mux_4x1_20 port map ("00000110010111101111", MODE(39 downto 20), decod_mux, "11111100011100111101", SEL_DISP, REG);
L5 : mux_2x1 port map (SW, MODE(9 downto 0), IN_POT, SEL_POT);
end SELETORES_bhv;
I've tested on ModelSim 10.1c with no problems.
I have a project to create an ALU with clock and reset signals, but for the following code this error appears "Illegal sequential statement". I think the problem is instantiating entities inside a process. How can i fix this?
library ieee;
use ieee.std_logic_1164.all;
entity alu is
port(a: in std_logic_vector(31 downto 0);
b: in std_logic_vector(31 downto 0);
c: in std_logic_vector(31 downto 0);
opcode: in std_logic_vector(2 downto 0);
rst: in std_logic;
cout: out std_logic;
output: out std_logic_vector(31 downto 0);
zero: out std_logic);
end alu;
architecture my_arch of alu is
component mux4to1_32bits
port (and_in: in std_logic_vector(31 downto 0);
not_in: in std_logic_vector(31 downto 0);
or_in: in std_logic_vector(31 downto 0);
xor_in: in std_logic_vector(31 downto 0);
sel: in std_logic_vector(1 downto 0);
f: out std_logic_vector(31 downto 0));
end component;
component mux2to1_32bits
port (in1: in std_logic_vector(31 downto 0);
in2: in std_logic_vector(31 downto 0);
sel: in std_logic;
output: out std_logic_vector(31 downto 0));
end component;
component full_adder_32bits
port (in_a: in std_logic_vector(31 downto 0);
in_b: in std_logic_vector(31 downto 0);
cin: in std_logic;
fa: out std_logic_vector(31 downto 0);
cout: out std_logic);
end component;
component and_32bits
port (in1: in std_logic_vector(31 downto 0);
in2: in std_logic_vector(31 downto 0);
output: out std_logic_vector(31 downto 0));
end component;
component or_32bits
port (in1: in std_logic_vector(31 downto 0);
in2: in std_logic_vector(31 downto 0);
output: out std_logic_vector(31 downto 0));
end component;
component not_32bits
port (in1: in std_logic_vector(31 downto 0);
output: out std_logic_vector(31 downto 0));
end component;
component xor_32bits
port (in1: in std_logic_vector(31 downto 0);
in2: in std_logic_vector(31 downto 0);
output: out std_logic_vector(31 downto 0));
end component;
component zero_flag
port ( result: in std_logic_vector(31 downto 0);
zf: out std_logic);
end component;
signal port_and: std_logic_vector(31 downto 0);
signal port_or: std_logic_vector(31 downto 0);
signal port_not: std_logic_vector(31 downto 0);
signal port_xor: std_logic_vector(31 downto 0);
signal port_not1: std_logic_vector(31 downto 0);
signal output_mux2to1: std_logic_vector(31 downto 0);
signal output_mux4to1: std_logic_vector(31 downto 0);
signal output_fa: std_logic_vector(31 downto 0);
signal mid_output: std_logic_vector(31 downto 0);
signal Clk : std_logic := '0';
constant Clk_period : time := 10 ns;
begin
Clk_process :process
begin
Clk <= '0';
wait for Clk_period/2;
Clk <= '1';
wait for Clk_period/2;
end process;
stim_proc: process
begin
wait for Clk_period*2;
and_port: and_32bits port map (a(31 downto 0),b(31 downto 0),port_and(31 downto 0));
not_port: not_32bits port map (a(31 downto 0),port_not(31 downto 0));
or_port: or_32bits port map (a(31 downto 0),b(31 downto 0),port_or(31 downto 0));
xor_port: xor_32bits port map (a(31 downto 0),b(31 downto 0),port_xor(31 downto 0));
not1_port: not_32bits port map (b(31 downto 0),port_not1(31 downto 0));
mux2to1_1: mux2to1_32bits port map (b(31 downto 0),port_not1(31 downto 0),opcode(0),output_mux2to1(31 downto 0));
mux4to1: mux4to1_32bits port map (port_and(31 downto 0),port_not(31 downto 0),port_or(31 downto 0),port_xor(31 downto 0),opcode(1 downto 0),output_mux4to1(31 downto 0));
fulladder: full_adder_32bits port map (a(31 downto 0),output_mux2to1(31 downto 0),opcode(0),output_fa(31 downto 0),cout);
mux2to1_2: mux2to1_32bits port map (output_fa(31 downto 0),output_mux4to1(31 downto 0),opcode(2),mid_output(31 downto 0));
zero_output: zero_flag port map (mid_output(31 downto 0),zero);
output <= mid_output;
wait;
end process;
end my_arch;
You are correct. You should instantiate your component's port maps outside the stim_proc. Think of or visualize this as next to, or along side your processes. It is just the wiring of signals between components and process circuits. Within the process you would have only the code that describes how the data moves across the signals that run between your processes and components.
When I try to compile this code I keep getting an error that says:
line 13: Error, 'std_logic' is not a known type.
Line 13 is Clock : IN std_logic;in the ALU_tb entity.
I am confused by this error, because it is my understanding that the reason for said error is normally a missing library/package. I'm almost sure I have the appropriate libraries and packages. Plus none of the other signals of type std_logic are getting errors.
If anyone could help me figure this out, I would greatly appreciate it.
-- VHDL Entity ALU.ALU_tb.symbol
--
-- Created:
-- by - ClarkG.UNKNOWN (COELABS15)
-- at - 19:58:20 09/ 8/2014
--
-- Generated by Mentor Graphics' HDL Designer(TM) 2011.1 (Build 18)
--
ENTITY ALU_tb IS
PORT(
Clock : IN std_logic;
Reset_N : IN std_logic
);
-- Declarations
END ALU_tb ;
--
-- VHDL Architecture ALU.ALU_tb.struct
--
-- Created:
-- by - ClarkG.UNKNOWN (COELABS15)
-- at - 19:58:20 09/ 8/2014
--
-- Generated by Mentor Graphics' HDL Designer(TM) 2011.1 (Build 18)
--
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.std_logic_arith.ALL;
LIBRARY ALU;
ARCHITECTURE struct OF ALU_tb IS
-- Architecture declarations
-- Internal signal declarations
SIGNAL A : std_logic_vector(31 DOWNTO 0);
SIGNAL ALUOp : std_logic_vector(3 DOWNTO 0);
SIGNAL B : std_logic_vector(31 DOWNTO 0);
SIGNAL Overflow : std_logic;
SIGNAL R : std_logic_vector(31 DOWNTO 0);
SIGNAL SHAMT : std_logic_vector(4 DOWNTO 0);
SIGNAL Zero : std_logic;
-- Component Declarations
COMPONENT ALU
PORT (
A : IN std_logic_vector (31 DOWNTO 0);
ALUOp : IN std_logic_vector (3 DOWNTO 0);
B : IN std_logic_vector (31 DOWNTO 0);
SHAMT : IN std_logic_vector (4 DOWNTO 0);
Overflow : OUT std_logic ;
R : OUT std_logic_vector (31 DOWNTO 0);
Zero : OUT std_logic
);
END COMPONENT;
COMPONENT ALU_tester
PORT (
A : IN std_logic_vector (31 DOWNTO 0);
ALUOp : IN std_logic_vector (3 DOWNTO 0);
B : IN std_logic_vector (31 DOWNTO 0);
Clock : IN std_logic ;
Overflow : IN std_logic ;
R : IN std_logic_vector (31 DOWNTO 0);
Reset_N : IN std_logic ;
SHAMT : IN std_logic_vector (4 DOWNTO 0);
Zero : IN std_logic
);
END COMPONENT;
COMPONENT Test_transaction_generator
PORT (
Clock : IN std_logic ;
A : OUT std_logic_vector (31 DOWNTO 0);
ALUOp : OUT std_logic_vector (3 DOWNTO 0);
B : OUT std_logic_vector (31 DOWNTO 0);
SHAMT : OUT std_logic_vector (4 DOWNTO 0)
);
END COMPONENT;
-- Optional embedded configurations
-- pragma synthesis_off
FOR ALL : ALU USE ENTITY ALU.ALU;
FOR ALL : ALU_tester USE ENTITY ALU.ALU_tester;
FOR ALL : Test_transaction_generator USE ENTITY ALU.Test_transaction_generator;
-- pragma synthesis_on
BEGIN
-- Instance port mappings.
U_0 : ALU
PORT MAP (
A => A,
ALUOp => ALUOp,
B => B,
SHAMT => SHAMT,
Overflow => Overflow,
R => R,
Zero => Zero
);
U_1 : ALU_tester
PORT MAP (
A => A,
ALUOp => ALUOp,
B => B,
Clock => Clock,
Overflow => Overflow,
R => R,
Reset_N => Reset_N,
SHAMT => SHAMT,
Zero => Zero
);
U_2 : Test_transaction_generator
PORT MAP (
Clock => Clock,
A => A,
ALUOp => ALUOp,
B => B,
SHAMT => SHAMT
);
END struct;
The context clause comprised of a library clauses and use clauses should be moved to before the entity declaration instead of just before the architecture body. An entity and an architecture form a common declarative region allowing those library and use clauses to be in effect across both instead of just the architecture, as in your code presently.
You also don't appear to be using package std_logic_arith in the code you've shown. (The architecture only contains components).
At line 13, you have not yet imported the ieee libraries required to define std_logic which is why you're getting the error.
i am new to vhdl. i have a code with me as follows (the sub prog compiles very fine). i can't fix the following error
** Error: C:/Users/acer/Desktop/alu new/ALU_VHDL.vhd(110): Illegal sequential statement.
** Error: C:/Users/acer/Desktop/alu new/ALU_VHDL.vhd(115): Illegal sequential statement.
** Error: C:/Users/acer/Desktop/alu new/ALU_VHDL.vhd(120): Illegal sequential statement.
** Error: C:/Users/acer/Desktop/alu new/ALU_VHDL.vhd(128): Illegal sequential statement.
** Warning: [14] C:/Users/acer/Desktop/alu new/ALU_VHDL.vhd(128): (vcom-1272) Length of formal "Remainder" is 4; length of actual is 8.
** Error: C:/Users/acer/Desktop/alu new/ALU_VHDL.vhd(138): VHDL Compiler exiting
the line nos are bold ones in the code here.they are the portmap ones
Can anyone please help me out with this. it would be very kind of you.
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
entity ALU_VHDL is
port
(
OperandA : in std_logic_vector(3 downto 0);
OperandB : in std_logic_vector(3 downto 0);
Operation: in std_logic_vector(2 downto 0);
Startt : in std_logic;
Ready : out std_logic;
Result_High : out std_logic_vector(3 downto 0);
Result_Low : out std_logic_vector(7 downto 0);
Errorsig : out std_logic;
Reset_n : in std_logic;
Clkk : in std_logic);
end entity ALU_VHDL;
architecture Behavioral of ALU_VHDL is
-- And gate
component AND_gate
port(
x,y : IN std_logic_vector(3 downto 0);
z : OUT std_logic_vector(3 downto 0));
end component;
-- OR Gate
component OR_gate
port(
x,y : IN std_logic_vector(3 downto 0);
z : OUT std_logic_vector(3 downto 0));
end component;
-- XOR gate
component XOR_gate
port(
x,y : IN std_logic_vector(3 downto 0);
z : OUT std_logic_vector(3 downto 0));
end component;
-- Adder
COMPONENT adder4
PORT
(
C : IN std_logic;
x,y : IN std_logic_vector(3 DOWNTO 0);
R : OUT std_logic_vector(3 DOWNTO 0);
C_out : OUT std_logic);
END COMPONENT;
-- Subtractor
COMPONENT Substractor4
PORT
(
br_in : IN std_logic;
x,y : IN std_logic_vector(3 DOWNTO 0);
R : OUT std_logic_vector(3 DOWNTO 0);
E : out std_logic);
END COMPONENT;
-- Multiplier
COMPONENT mult4by4
port(operA, operB: in std_logic_vector(3 downto 0);
sumOut: out std_logic_vector(7 downto 0));
END COMPONENT;
-- Division
COMPONENT Division
Port ( Dividend : in std_logic_vector(3 downto 0);
Divisor : in std_logic_vector(3 downto 0);
Start : in std_logic;
Clk : in std_logic;
Quotient : out std_logic_vector(3 downto 0);
Remainder : out std_logic_vector(3 downto 0);
Finish : out std_logic);
END COMPONENT;
begin
process(OperandA, OperandB, Startt, Operation) is
begin
case Operation is
when "000" =>
Result_High <= "XXXX";
when "001" =>
Result_High <= OperandA and OperandB;
when "010" =>
Result_High <= OperandA or OperandB;
when "011" =>
Result_High <= OperandA xor OperandB;
when "100" =>
-- Adder
**U05 : adder4 PORT MAP (C=>Startt,x=>OperandA,y=>OperandB,R=>Result_High,C_out=>Ready);**
when "101" =>
-- Substractor & Error signal
**U06 : Substractor4 PORT MAP (br_in=>Startt,x=>OperandA,y=>OperandB,R=>Result_High,E=>Errorsig);**
when "110" =>
-- multiplication
**U07 : mult4by4 PORT MAP (operA=>OperandA,operB=>OperandB,sumOut=>Result_Low);**
when "111" =>
-- Division
if (OperandB ="0000") then
Errorsig <= '1';
else
**U08 : Division PORT MAP (Dividend=>OperandA,Divisor=>OperandB,Start=>Startt,Clk=>Clkk,Quotient=>Result_High,Remainder=>Result_Low,Finish=>Ready);**
end if;
when others =>
Errorsig <= '1';
end case;
end process;
end architecture Behavioral;
You cannot instantiate entities within a process.
Move all entity instantiations out of the process (into the architecture body) and work from there.
If you want to in instantiate component depending on the value of 'Operation', like the zennehoy wrote, you should instantiate components out of the process and in this case statement only use signal connected to this components in instantiations and link it to port you want.
For the length issue change the "Remainder : out std_logic_vector(3 downto 0);"
to "Remainder : out std_logic_vector(7 downto 0);"