The following code contains a vhdl file and a test bench for it.
Main file
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity lici is
port(PT_MSB : in std_logic_vector(31 downto 0);
PT_LSB: in std_logic_vector( 31 downto 0);
--key: in std_logic_vector(127 downto 0);
RK1: in std_logic_vector(31 downto 0);
RK2: in std_logic_vector(31 downto 0);
clk: in std_logic;
CT_LSB: out std_logic_vector(31 downto 0);
CT_MSB: out std_logic_vector(31 downto 0);
check: out std_logic_vector(31 downto 0)
);
end lici;
architecture beh of lici is
type S_BOX is array(15 downto 0)of std_logic_vector(3 downto 0);
signal sub: S_BOX:=(0=>x"3",1=>x"F",2=>x"E",3=>x"1",4=>x"0",5=>x"A",6=>x"5",7=>x"8",8=>x"c",9=>x"4",10=>x"B",11=>x"2",12=>x"9",13=>x"7",14=>x"6",15=>x"D");
begin
process(clk)
Variable var_PT_MSB : std_logic_vector(31 downto 0);
variable var_PT_LSB : std_logic_vector( 31 downto 0);
variable var_EN_PT_MSB: std_logic_vector(31 downto 0);
variable var_XOR_RK_SHR7: std_logic_vector(31 downto 0);
variable var_XOR_SHL3: std_logic_vector(31 downto 0);
variable var_CT_LSB: std_logic_vector(31 downto 0);
variable S_data: std_logic_vector(3 downto 0);
variable outside_counter: natural:= 0;
variable i: natural:= 1;
begin
var_PT_MSB:= PT_MSB;
var_PT_LSB:= PT_LSB;
if(outside_counter< 31) then
if(clk'event and clk='1' and i <= 8) then
S_data:= (var_PT_MSB(31 downto 28) and x"F");
case S_data is
when x"0"=> var_EN_PT_MSB(35-(i*4) downto 32-(i*4)):=sub(0);
when x"1"=> var_EN_PT_MSB(35-(i*4) downto 32-(i*4)):=sub(1);
when x"2"=> var_EN_PT_MSB(35-(i*4) downto 32-(i*4)):=sub(2);
when x"3"=> var_EN_PT_MSB(35-(i*4) downto 32-(i*4)):=sub(3);
when x"4"=> var_EN_PT_MSB(35-(i*4) downto 32-(i*4)):=sub(4);
when x"5"=> var_EN_PT_MSB(35-(i*4) downto 32-(i*4)):=sub(5);
when x"6"=> var_EN_PT_MSB(35-(i*4) downto 32-(i*4)):=sub(6);
when x"7"=> var_EN_PT_MSB(35-(i*4) downto 32-(i*4)):=sub(7);
when x"8"=> var_EN_PT_MSB(35-(i*4) downto 32-(i*4)):=sub(8);
when x"9"=> var_EN_PT_MSB(35-(i*4) downto 32-(i*4)):=sub(9);
when x"A"=> var_EN_PT_MSB(35-(i*4) downto 32-(i*4)):=sub(10);
when x"B"=> var_EN_PT_MSB(35-(i*4) downto 32-(i*4)):=sub(11);
when x"C"=> var_EN_PT_MSB(35-(i*4) downto 32-(i*4)):=sub(12);
when x"D"=> var_EN_PT_MSB(35-(i*4) downto 32-(i*4)):=sub(13);
when x"E"=> var_EN_PT_MSB(35-(i*4) downto 32-(i*4)):=sub(14);
when others=>var_EN_PT_MSB(35-(i*4) downto 32-(i*4)):=sub(15);
end case;
var_PT_MSB:= std_logic_vector(shift_left(unsigned(var_PT_MSB),4));
i:=i+1;
end if;
var_XOR_SHL3:= var_EN_PT_MSB xor RK1 xor var_PT_LSB;
var_XOR_SHL3:= std_logic_vector(rotate_left(unsigned(var_XOR_SHL3),3));
var_XOR_RK_SHR7:= var_EN_PT_MSB xor RK2 xor var_XOR_SHL3;
CT_LSB<= std_logic_vector(rotate_right(unsigned(var_XOR_RK_SHR7),7));
var_CT_LSB:= std_logic_vector(rotate_right(unsigned(var_XOR_RK_SHR7),7));
CT_MSB<= var_XOR_SHL3;
var_PT_MSB:= var_XOR_SHL3;
var_PT_LSB:= var_CT_LSB;
check<= var_EN_PT_MSB;
outside_counter:= outside_counter+1;
end if;
end process;
end beh;
--------------------------------------------------------------------------
This is the test bench for it
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity lici_tb is
end lici_tb;
architecture behav of lici_tb is
component lici is
port(PT_MSB : in std_logic_vector(31 downto 0);
PT_LSB: in std_logic_vector( 31 downto 0);
RK1: in std_logic_vector(31 downto 0);
RK2: in std_logic_vector(31 downto 0);
clk: in std_logic;
CT_LSB: out std_logic_vector (31 downto 0);
CT_MSB: out std_logic_vector(31 downto 0);
check: out std_logic_vector(31 downto 0)
);
end component;
signal clk :std_logic := '0';
signal PT_MSB:std_logic_vector(31 downto 0):=x"ABCDEF01";
signal PT_LSB:std_logic_vector( 31 downto 0):=x"23456789";
signal RK1:std_logic_vector(31 downto 0):=x"00000010";
signal RK2:std_logic_vector(31 downto 0):= x"00000001";
signal CT_LSB:std_logic_vector(31 downto 0);
signal CT_MSB: std_logic_vector(31 downto 0);
signal check: std_logic_vector(31 downto 0);
constant CLK_PERIOD : time := 10 ns;
begin
uut : lici port map (
PT_MSB => PT_MSB,
PT_LSB=>PT_LSB,
RK1=>RK1,
RK2=> RK2,
clk => clk,
CT_LSB=>CT_LSB,
CT_MSB => CT_MSB,
check=>check
);
Clk_process :process
begin
clk <= '0';
wait for CLK_PERIOD/2; --for half of clock period clk stays at '0'.
clk <= '1';
wait for CLK_PERIOD/2; --for next half of clock period clk stays at '1'.
end process;
end;
At the end I need to have 31 values in CT_LSB and CT_MSB.
In each cycle I wish to have different encrypted values in CT_LSB and CT_MSB,
In one cycle one iteration of outside_counter needs to happen in which 8 NIBBLE has to encrypted.
This entire code needs to work without using a For Loops.
Can someone help me with this?
Related
I have sliced a 16 bit STD_LOGIC_VECTOR into 3 parts. I want to leave the first 8 MSBs untouched and break the 8 LSBs into 2 nibbles to do some processing on them.
I can do all this and the processing is all fine but when I try to put them all together into a 16 bit STD_LOGIC_VECTOR output it just stays UUUU. is there a special way that putting it back together should go?
signal fullout : std_logic_vector(15 downto 0);
signal Sbox1 : integer;
signal Sbox2 : integer;
signal tophalf : std_logic_vector(7 downto 0);
signal secondnibble, firstnibble : std_logic_vector(3 downto 0); --break the LSH into 2 nibbles
begin
tophalf(7 downto 0) <= LUTin(15 downto 8);
secondnibble(3 downto 0) <= LUTin(7 downto 4);
-- Sbox1 <= to_integer(unsigned(secondnibble));
firstnibble(3 downto 0) <= LUTin(3 downto 0);
-- Sbox2 <= to_integer(unsigned(firstnibble));
p1: process(LUTin)
begin
fullout(15 downto 8) <= tophalf(7 downto 0);
fullout(7 downto 4) <= secondnibble(3 downto 0);
fullout(3 downto 0) <= firstnibble(3 downto 0);
Always initialize outputs. In your case, its not clear that what is output, so here is my guess:
architecture xyz of zyx is
signal fullout : std_logic_vector(15 downto 0) := (others =>'0');
signal tophalf : std_logic_vector(7 downto 0):= (others =>'0');
signal secondnibble, firstnibble : std_logic_vector(3 downto 0):= (others =>'0');
.....
begin
....
end xyz;
1.8-bit multiplier
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity M8 is
Port ( M1 : in STD_LOGIC_vector(7 downto 0);
M2 : in STD_LOGIC_vector(7 downto 0);
Mout : out STD_LOGIC_vector(15 downto 0)
);
end M8;
architecture Behavioral of M8 is
begin
process(M1,M2)
variable A1: std_logic_vector(17 downto 0);
begin
A1(17 downto 0) := "0000000000" & M1(7 downto 0);
for N in 1 to 9 loop
if A1(0)='1' then
A1(17 downto 9) := A1(17 downto 9) + '0'+ M2(7 downto 0);
end if;
A1(17 downto 0) := '0' & A1(17 downto 1);
end loop;
Mout<= A1(15 downto 0);
end process;
end Behavioral;
2.32-bit multiplier
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity M32 is
Port ( M1 : in STD_LOGIC_vector(31 downto 0);
M2 : in STD_LOGIC_vector(31 downto 0);
Mout : out STD_LOGIC_vector(63 downto 0)
);
end M32;
architecture Behavioral of M32 is
begin
process(M1,M2)
variable A1: std_logic_vector(65 downto 0);
begin
A1(65 downto 0) := "0000000000000000000000000000000000" & M1(31 downto 0);
for N in 1 to 33 loop
if A1(0)='1' then
A1(65 downto 33) := A1(65 downto 33) + '0'+ M2(31 downto 0);
end if;
A1(65 downto 0) := '0' & A1(65 downto 1);
end loop;
Mout<= A1(63 downto 0);
end process;
end Behavioral;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity MM32All is
port( MMM1: in std_logic_vector(31 downto 0);
MMM2: in std_logic_vector(31 downto 0);
MMMout: out std_logic_vector(63 downto 0)
);
end MM32All;
architecture Behavioral of MM32All is
component M32 port(MM1 : in std_logic_vector(31 downto 0);
MM2 : in std_logic_vector(7 downto 0);
MMout:out std_logic_vector(39 downto 0)
);
end component;
signal MMb: std_logic_vector(31 downto 0);
signal MMa: std_logic_vector(31 downto 0);
signal MMo1: std_logic_vector(39 downto 0);
signal MMo2: std_logic_vector(39 downto 0);
signal MMo3: std_logic_vector(39 downto 0);
signal MMo4: std_logic_vector(39 downto 0);
signal MMout1: std_logic_vector(63 downto 0);
begin
Ma4: M32 port map (MM1=> MMb, MM2=> MMa(31 downto 24), MMout=> MMo4);
Ma3: M32 port map (MM1=> MMb, MM2=> MMa(23 downto 16), MMout=> MMo3);
Ma2: M32 port map (MM1=> MMb, MM2=> MMa(15 downto 8) , MMout=> MMo2);
Ma1: M32 port map (MM1=> MMb, MM2=> MMa(7 downto 0 ) , MMout=> MMo1);
MMout1 <= ("000000000000000000000000" & MMo1) + ("0000000000000000" & MMo2 & "00000000")
+ ("00000000" & MMo3 & "0000000000000000" ) + ( MMo4 & "000000000000000000000000" );
MMb <= MMM1;
MMa <= MMM2;
MMMout <= MMout1;
end Behavioral;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity M32 is
port(MM1 : in std_logic_vector(31 downto 0);
MM2 : in std_logic_vector(7 downto 0);
MMout:out std_logic_vector(39 downto 0)
);
end M32;
architecture Behavioral of M32 is
component M8 Port ( M1 : in STD_LOGIC_vector(7 downto 0);
M2 : in STD_LOGIC_vector(7 downto 0);
Mout : out STD_LOGIC_vector(15 downto 0)
);
end component;
component M8b Port ( M1 : in STD_LOGIC_vector(7 downto 0);
M2 : in STD_LOGIC_vector(7 downto 0);
Mout : out STD_LOGIC_vector(15 downto 0)
);
end component;
component M8c Port ( M1 : in STD_LOGIC_vector(7 downto 0);
M2 : in STD_LOGIC_vector(7 downto 0);
Mout : out STD_LOGIC_vector(15 downto 0)
);
end component;
component M8d Port ( M1 : in STD_LOGIC_vector(7 downto 0);
M2 : in STD_LOGIC_vector(7 downto 0);
Mout : out STD_LOGIC_vector(15 downto 0)
);
end component;
signal internalMM1: std_logic_vector(31 downto 0);
signal internalMM2: std_logic_vector(7 downto 0);
signal internalMMout: std_logic_vector(39 downto 0);
signal M8dout:std_logic_vector(15 downto 0);
signal M8cout:std_logic_vector(15 downto 0);
signal M8bout:std_logic_vector(15 downto 0);
signal M8out:std_logic_vector(15 downto 0);
begin
--addres: for N in 0 to 3 generate
FulMd32: M8d port map( M1=> internalMM1(31 downto 24), M2=> internalMM2, Mout=> M8dout);
FulMb32: M8b port map( M1=> internalMM1(23 downto 16), M2=> internalMM2, Mout=> M8cout);
FulMc32: M8c port map( M1=> internalMM1(15 downto 8), M2=> internalMM2, Mout=> M8bout);
FulM32: M8 port map( M1=> internalMM1(7 downto 0), M2=> internalMM2, Mout=> M8out);
internalMMout<=("000000000000000000000000" & M8out)
+ ("0000000000000000" & M8bout & "00000000") + ("00000000" & M8cout & "0000000000000000")
+ (M8dout & "000000000000000000000000");
internalMM1 <= MM1;
internalMM2 <= MM2;
MMout <= internalMMout;
end Behavioral;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
entity ALU is
port( A :in std_logic_vector(31 downto 0);
B :in std_logic_vector(31 downto 0);
SS:in std_logic_vector(2 downto 0);
C :out std_logic_vector(63 downto 0);
D :out std_logic_vector(31 downto 0);
La,Sm,Eq: out std_logic);
end ALU;
architecture Behavioral of ALU is
Component M32 is port (M1 : in STD_LOGIC_vector(31 downto 0);
M2 : in STD_LOGIC_vector(31 downto 0);
Mout : out STD_LOGIC_vector(63 downto 0));
end component;
Component SUB32 is port(A : in STD_LOGIC_vector(31 downto 0);
B : in STD_LOGIC_vector(31 downto 0);
OFL:out std_logic;
S : out STD_LOGIC_vector(31 downto 0));
end component;
Component adder32 is Port(A : in STD_LOGIC_vector(31 downto 0);
B : in STD_LOGIC_vector(31 downto 0);
Cin : in STD_LOGIC;
Cout : out STD_LOGIC;
S : out STD_LOGIC_vector(31 downto 0));
end component;
signal aM1,aM2,bM1,bM2,cM1,cM2,cMout,bMout : STD_LOGIC_vector(31 downto 0);
signal aMout: STD_LOGIC_vector(63 downto 0);
signal Overflow: std_logic;
begin
A1: M32 port map( M1=> aM1, M2=>aM2, Mout=>aMout);
A2: SUB32 port map(A=> bM1, B=> bM2, S=>bMout, OFL=>Overflow);
A3: adder32 port map(A=> cM1, B=> cM2, Cout=>open,S=>cMout,Cin=>'0');
process(SS,A,B,Overflow,aMout,bMout,CMout)
begin
Case SS is
When "000"=> aM1<=A;
aM2<=B;
C<=aMout;
When "001" => if Overflow='1' then
bM1<=A;
bM2<=B;
D<=bMout;
else
D<="00000000000000000000000000000000";
end if;
when "010" => cM1<=A;
cM2<=B;
D<= cMout;
when "011" => if (A > B) then
La<='1';
Sm<='0';
Eq<='0';
else if (A<B) then
La<='0';
Sm<='1';
Eq<='0';
else
La<='0';
Sm<='0';
Eq<='1';
end if;
end if;
when "100" =>
D <= (A and B);
when "101" =>
D <= (A or B);
when "110" =>
D <= (A xor B);
When others=> C<="ZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZ";
D<="ZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZ";
end case;
end process;
end Behavioral;
32-bit ALU
Based on the Device utilization summary, two designs of multiplier have very similar area utilization. 32-bit multiplier by 8-bit multiplier use about 5% more logic unit than single 32-bit multiplier. The number of used route thru used for 32-bit multiplier by 8-bit multiplier is 238% of single 32-bit multiplier. Even use different design, their performance are the same.
You have very obscure way of doing multiplier as scary_jeff indicates. Most likely the synthesis tool gets confused about that.
Instead of
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
Please have
use ieee.numeric_std.all;
and instead of
std_logic_vector(n-1 downto 0)
use
signed(n-1 downto 0);
Then you can just multiply with *.
Off topic, but instead of
D<="00000000000000000000000000000000";
you can use
D <= (others => '0');
I want make menu choice
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
ENTITY aluall IS
PORT(
A:IN STD_LOGIC_VECTOR(7 DOWNTO 0);
B:IN STD_LOGIC_VECTOR(7 DOWNTO 0);
CLK:IN STD_LOGIC;
LOAD: in std_logic;
RESET: IN STD_LOGIC;
D:OUT STD_LOGIC_VECTOR(7 DOWNTO 0));
END aluall;
ARCHITECTURE structual OF aluall IS
SIGNAL finor,Rsub2,Rsub,Radd,Radd2,Radd1 : STD_LOGIC_VECTOR(7 DOWNTO 0);
SIGNAL rAnd : STD_LOGIC_VECTOR(7 DOWNTO 0);
signal rePiso : std_logic;
SIGNAL fmulti : STD_LOGIC_VECTOR(15 DOWNTO 0);
SIGNAL compare: STD_LOGIC_VECTOR(1 DOWNTO 0);
signal repo: std_logic_vector(7 downto 0);
signal choice: integer range 0 to 10;
COMPONENT orGate
PORT( A:IN STD_LOGIC_VECTOR(7 DOWNTO 0);
B:IN STD_LOGIC_VECTOR(7 DOWNTO 0);
F:OUT STD_LOGIC_VECTOR(7 DOWNTO 0));
END COMPONENT;
COMPONENT andGate
PORT( A:IN STD_LOGIC_VECTOR(7 DOWNTO 0);
B:IN STD_LOGIC_VECTOR(7 DOWNTO 0);
F:OUT STD_LOGIC_VECTOR(7 DOWNTO 0));
END COMPONENT;
COMPONENT add1
PORT(
A : in std_logic_vector(7 downto 0);
C : out std_logic_vector(7 downto 0));
END COMPONENT;
COMPONENT add2
port(
B : in std_logic_vector(7 downto 0);
C : out std_logic_vector(7 downto 0));
END COMPONENT;
COMPONENT add
port(
A : in std_logic_vector(7 downto 0);
B : in std_logic_vector(7 downto 0);
C : out std_logic_vector(7 downto 0));
END COMPONENT;
BEGIN --i want make choice menu for what go to output
process(A,B,choice)
begin
if(choice = 0) then
label0: andGate PORT MAP (A,B,rAnd);
else
label1: orGate PORT MAP (A,B,finor);
end if;
label2: add PORT MAP (A,B,Radd);
label3: sub PORT MAP (A,B,Rsub);
label4: sub2 PORT MAP (A,B,Rsub2);
end structual;
I have error Illegal sequential statement.
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
ENTITY aluall IS
PORT(
A:IN STD_LOGIC_VECTOR(7 DOWNTO 0);
B:IN STD_LOGIC_VECTOR(7 DOWNTO 0);
code : std_logic_vector(3 downto 0);
CLK:IN STD_LOGIC;
D:OUT STD_LOGIC_VECTOR(7 DOWNTO 0));
END aluall;
ARCHITECTURE structual OF aluall IS
SIGNAL finor,Rsub2,Rsub,Radd,Radd2,Radd1 : STD_LOGIC_VECTOR(7 DOWNTO 0);
SIGNAL rAnd : STD_LOGIC_VECTOR(7 DOWNTO 0);
signal rePiso : std_logic;
SIGNAL fmulti : STD_LOGIC_VECTOR(15 DOWNTO 0);
SIGNAL compare: STD_LOGIC_VECTOR(7 DOWNTO 0);
signal repo: std_logic_vector(7 downto 0);
COMPONENT orGate
PORT( A:IN STD_LOGIC_VECTOR(7 DOWNTO 0);
B:IN STD_LOGIC_VECTOR(7 DOWNTO 0);
F:OUT STD_LOGIC_VECTOR(7 DOWNTO 0));
END COMPONENT;
COMPONENT andGate
PORT( A:IN STD_LOGIC_VECTOR(7 DOWNTO 0);
B:IN STD_LOGIC_VECTOR(7 DOWNTO 0);
F:OUT STD_LOGIC_VECTOR(7 DOWNTO 0));
END COMPONENT;
COMPONENT add1
PORT(
A : in std_logic_vector(7 downto 0);
C : out std_logic_vector(7 downto 0));
END COMPONENT;
COMPONENT add2
port(
B : in std_logic_vector(7 downto 0);
C : out std_logic_vector(7 downto 0));
END COMPONENT;
COMPONENT multi
port(
A : in std_logic_vector(7 downto 0);
B : in std_logic_vector(7 downto 0);
C : out std_logic_vector(15 downto 0));
END COMPONENT;
COMPONENT add
port(
A : in std_logic_vector(7 downto 0);
B : in std_logic_vector(7 downto 0);
C : out std_logic_vector(7 downto 0));
END COMPONENT;
COMPONENT sub
port(
A : in std_logic_vector(7 downto 0);
B : in std_logic_vector(7 downto 0);
C : out std_logic_vector(7 downto 0));
END COMPONENT;
COMPONENT sub2
port(
A : in std_logic_vector(7 downto 0);
B : in std_logic_vector(7 downto 0);
C : out std_logic_vector(7 downto 0));
END COMPONENT;
COMPONENT comparing
port(
A : in std_logic_vector(7 downto 0);
B : in std_logic_vector(7 downto 0);
C : out std_logic_vector(7 downto 0)
);
END COMPONENT;
COMPONENT piso
port(
CLK,LOAD : in std_logic;
PI : in std_logic_vector(7 downto 0);
SO : out std_logic
);
END COMPONENT;
COMPONENT pipo
port(
clk:in std_logic;
pi: in std_logic_vector(7 downto 0);
po:out std_logic_vector(7 downto 0)
);
end COMPONENT;
begin
label0: andGate PORT MAP (A,B,rAnd);
label1: orGate PORT MAP (A,B,finor);
label2: add PORT MAP (A,B,Radd);
label3: sub PORT MAP (A,B,Rsub);
label4: sub2 PORT MAP (A,B,Rsub2);
label5: add1 PORT MAP (A,Radd1);
label6: add2 PORT MAP (B,Radd2);
label7: multi PORT MAP (A,B,fmulti);
label8: comparing PORT MAP (A,B,compare);
process(A,B,CLK,code)
begin
if (code = "0000") then
D<= rAnd;
elsif(code ="0001") then
D<= finor;
elsif(code ="0010") then
D<=Rsub;
elsif(code = "0011") then
D<=Radd;
elsif(code = "0100") then
D<=Rsub;
elsif(code = "0101") then
D<=Rsub2;
elsif(code = "0110") then
D<=Radd1;
elsif(code = "0111") then
D<=Radd2;
elsif(code = "1000") then
D<=fmulti;
else
D<=compare;
end if;
end process;
end structual;
i run this code and always run first if and last...why?
enter image description here
I have a project to create an ALU with clock and reset signals, but for the following code this error appears "Illegal sequential statement". I think the problem is instantiating entities inside a process. How can i fix this?
library ieee;
use ieee.std_logic_1164.all;
entity alu is
port(a: in std_logic_vector(31 downto 0);
b: in std_logic_vector(31 downto 0);
c: in std_logic_vector(31 downto 0);
opcode: in std_logic_vector(2 downto 0);
rst: in std_logic;
cout: out std_logic;
output: out std_logic_vector(31 downto 0);
zero: out std_logic);
end alu;
architecture my_arch of alu is
component mux4to1_32bits
port (and_in: in std_logic_vector(31 downto 0);
not_in: in std_logic_vector(31 downto 0);
or_in: in std_logic_vector(31 downto 0);
xor_in: in std_logic_vector(31 downto 0);
sel: in std_logic_vector(1 downto 0);
f: out std_logic_vector(31 downto 0));
end component;
component mux2to1_32bits
port (in1: in std_logic_vector(31 downto 0);
in2: in std_logic_vector(31 downto 0);
sel: in std_logic;
output: out std_logic_vector(31 downto 0));
end component;
component full_adder_32bits
port (in_a: in std_logic_vector(31 downto 0);
in_b: in std_logic_vector(31 downto 0);
cin: in std_logic;
fa: out std_logic_vector(31 downto 0);
cout: out std_logic);
end component;
component and_32bits
port (in1: in std_logic_vector(31 downto 0);
in2: in std_logic_vector(31 downto 0);
output: out std_logic_vector(31 downto 0));
end component;
component or_32bits
port (in1: in std_logic_vector(31 downto 0);
in2: in std_logic_vector(31 downto 0);
output: out std_logic_vector(31 downto 0));
end component;
component not_32bits
port (in1: in std_logic_vector(31 downto 0);
output: out std_logic_vector(31 downto 0));
end component;
component xor_32bits
port (in1: in std_logic_vector(31 downto 0);
in2: in std_logic_vector(31 downto 0);
output: out std_logic_vector(31 downto 0));
end component;
component zero_flag
port ( result: in std_logic_vector(31 downto 0);
zf: out std_logic);
end component;
signal port_and: std_logic_vector(31 downto 0);
signal port_or: std_logic_vector(31 downto 0);
signal port_not: std_logic_vector(31 downto 0);
signal port_xor: std_logic_vector(31 downto 0);
signal port_not1: std_logic_vector(31 downto 0);
signal output_mux2to1: std_logic_vector(31 downto 0);
signal output_mux4to1: std_logic_vector(31 downto 0);
signal output_fa: std_logic_vector(31 downto 0);
signal mid_output: std_logic_vector(31 downto 0);
signal Clk : std_logic := '0';
constant Clk_period : time := 10 ns;
begin
Clk_process :process
begin
Clk <= '0';
wait for Clk_period/2;
Clk <= '1';
wait for Clk_period/2;
end process;
stim_proc: process
begin
wait for Clk_period*2;
and_port: and_32bits port map (a(31 downto 0),b(31 downto 0),port_and(31 downto 0));
not_port: not_32bits port map (a(31 downto 0),port_not(31 downto 0));
or_port: or_32bits port map (a(31 downto 0),b(31 downto 0),port_or(31 downto 0));
xor_port: xor_32bits port map (a(31 downto 0),b(31 downto 0),port_xor(31 downto 0));
not1_port: not_32bits port map (b(31 downto 0),port_not1(31 downto 0));
mux2to1_1: mux2to1_32bits port map (b(31 downto 0),port_not1(31 downto 0),opcode(0),output_mux2to1(31 downto 0));
mux4to1: mux4to1_32bits port map (port_and(31 downto 0),port_not(31 downto 0),port_or(31 downto 0),port_xor(31 downto 0),opcode(1 downto 0),output_mux4to1(31 downto 0));
fulladder: full_adder_32bits port map (a(31 downto 0),output_mux2to1(31 downto 0),opcode(0),output_fa(31 downto 0),cout);
mux2to1_2: mux2to1_32bits port map (output_fa(31 downto 0),output_mux4to1(31 downto 0),opcode(2),mid_output(31 downto 0));
zero_output: zero_flag port map (mid_output(31 downto 0),zero);
output <= mid_output;
wait;
end process;
end my_arch;
You are correct. You should instantiate your component's port maps outside the stim_proc. Think of or visualize this as next to, or along side your processes. It is just the wiring of signals between components and process circuits. Within the process you would have only the code that describes how the data moves across the signals that run between your processes and components.
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_arith.all;
entity buffer_d_e is
port(
clk:in std_logic;
clr:in std_logic;
in_RegDst:in std_logic;
out_RegDst:out std_logic;
in_MemRead:in std_logic;
out_MemRead:out std_logic;
in_MemtoReg:in std_logic;
out_MemtoReg:out std_logic;
in_MemWrite:in std_logic;
out_MemWrite:out std_logic;
in_ALUop:in std_logic_vector(1 downto 0);
out_ALUop:out std_logic_vector(1 downto 0);
in_ALUsrc:in std_logic;
out_ALUsrc:out std_logic;
in_RegWrite:in std_logic;
out_RegWrite:out std_logic;
in_read_data_1:in std_logic_vector(31 downto 0);
out_read_data_1:out std_logic_vector(31 downto 0);
in_read_data_2:in std_logic_vector(31 downto 0);
out_read_data_2:out std_logic_vector(31 downto 0);
in_sign_ext:in std_logic_vector(31 downto 0);
out_sign_ext:out std_logic_vector(31 downto 0);
in_func:in std_logic_vector(5 downto 0);
out_func:out std_logic_vector(5 downto 0);
in_instr_20_16:in std_logic_vector(4 downto 0);
out_instr_20_16:out std_logic_vector(4 downto 0);
in_instr_15_11:in std_logic_vector(4 downto 0);
out_instr_15_11:out std_logic_vector(4 downto 0);
in_instr_25_21:in std_logic_vector(4 downto 0);
out_instr_25_21:out std_logic_vector(4 downto 0)
);
end buffer_d_e;
architecture behavioral of buffer_d_e is
signal s_RegDst,s_MemRead,s_MemtoReg,s_MemWrite,s_ALUsrc,s_RegWrite:std_logic;
signal s_ALUop:std_logic_vector(1 downto 0);
signal s_instr_20_16,s_instr_15_11,s_instr_25_21:std_logic_vector(4 downto 0);
signal s_func:std_logic_vector(5 downto 0);
signal s_read_data_1,s_read_data_2,s_sign_ext:std_logic_vector(31 downto 0);
begin
process(clk,clr)
begin
if clr='1'
then
s_RegDst<='X';
s_MemRead<='X';
s_MemtoReg<='X';
s_MemWrite<='X';
s_ALUop<="XX";
s_ALUsrc<='X';
s_RegWrite<='X';
s_read_data_1<="XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX";
s_read_data_2<="XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX";
s_sign_ext<="XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX";
s_func<="XXXXXX";
s_instr_20_16<="XXXXX";
s_instr_15_11<="XXXXX";
s_instr_25_21<="XXXXX";
elsif clk'event AND clk='1'
THEN
s_RegDst<=in_RegDst;
s_MemRead<=in_MemRead;
s_MemtoReg<=in_MemtoReg;
s_MemWrite<=in_MemWrite;
s_ALUop<=in_ALUop;
s_ALUsrc<=in_ALUsrc;
s_RegWrite<=in_RegWrite;
s_read_data_1<=in_read_data_1;
s_read_data_2<=in_read_data_2;
s_sign_ext<=in_sign_ext;
s_func<=in_func;
s_instr_20_16<=in_instr_20_16;
s_instr_15_11<=in_instr_15_11;
s_instr_25_21<=in_instr_25_21;
end if;
out_RegDst<=s_RegDst;
out_MemRead<=s_MemRead;
out_MemtoReg<=s_MemtoReg;
out_MemWrite<=s_MemWrite;
out_ALUop<=s_ALUop;
out_ALUsrc<=s_ALUsrc;
out_RegWrite<=s_RegWrite;
out_read_data_1<=s_read_data_1;
out_read_data_2<=s_read_data_2;
out_sign_ext<=s_sign_ext;
out_func<=s_func;
out_instr_20_16<=s_instr_20_16;
out_instr_15_11<=s_instr_15_11;
out_instr_25_21<=s_instr_25_21;
end process;
end behavioral;
Code above is a simple code for buffer. 'clr' is a clear signal, 'clk'is a clock. My confusion is that the simulation result of this buffer shows the input and output time interval is 1.5 clock cycle rather than 1 clock cycle.(s_addr1_same and s_rse are input and output of buffer respectively) But why it happens and how to solve this? Thanks in advance.