By default, when running make to compile a C source code file named prog.c
make prog
the default command that executes is
cc prog.c -o prog
Sometimes I really need to include some additional flags. I know that when there are no Makefiles, make relies on some environment variables.
On Ubuntu 14.04, how to configure these variables to change the command that gets executed by default?
Step by step answers will be appreciated!
When no makefile is present (or no rule exists in that makefile) make relies on a default built-in database of rules. Run make -p to get make to spit out all the rules it knows about (in the no makefile case that will be the default ones).
When you look at that list you will find a pattern rule for building C source into object files or executables. Those rules have variables in them (like CFLAGS, LDFLAGS, etc.) that can be used to control exactly what you are trying to. That's why they are there (and are why that default command has such funny spacing, in case you ever wondered about that).
Related
In Unix Makefile I can prefix a recipe line with - to ignore any error that will occur (as describe in Errors in Recipes).
hello_world: hello_world.cxx
-$(CXX) $(CXXFLAGS) $^ -o $#
I converted my Makefile to CMake:
cmake_minimum_required(VERSION 3.0)
project(HelloWorld)
add_executable(hello_world hello_world.cxx)
and run cmake and the generated Makefile looking fine, except the missing -.
Is it possible to generate Unix Makefile with CMake that will ignore errors (prefix the recipe line with -)?
The best would be to specify it per target level. I know I can run make -i to have the same behaviour but it isn't that convenient.
You cannot.
make is designed to give the user a fine control over commands it runs. CMake's under-the-hood commands are supposed to always succeed.
As a hack, you can generate makefiles and run make --ignore-errors.
But I advice making each of your examples that would fail a separate project, and run them from an external script.
I have a golang CLI program which generates a makefile to a specific project. While this works, there is an issue when the project already has a makefile. Of course I can check that in advance to avoid collusion, but how is it suggested to do it?
I'm not an expert in makefiles, but how can I create second makefile (maybe with the project name or something) that user can run via make (I guess with additional steps or info to the terminal)
You can generate it as Makefile.project and document to be run as make -f Makefile.project
You can give your Makefile whatever filename. Then make must be executed with parameter -f <your_filename> or --file=<your_filename>. See make manual on filenames.
Which version of make are you using? Some versions run special makefiles before others. For example, GNU make looks for the following files and runs the first one it finds: GNUmakefile, Makefile, makefile.
If you are using GNU make, then name your generated file GNUmakefile and add in the making any makefile already in the directory. That way, anyone running make in the directory will automatically run the generated makefike first.
Say I have compiled a project (not my own) with autotools and passed some flags to configure. Now I want to compile this same project again, but with slightly different configure flags. Is there a way to tell the configure script to use the old flags, but update them with some additional ones?
I would love to see an easier approach, but to simply add flags you can do:
sed -i '/^ac_configure_extra_args=/s/$/--new-flag --other-flag/' config.status
./config.status --recheck
Normally, I manually edit config.status to do this, and not all sed support -i, but you get the idea. Change the original flags as they are defined in config.status to be the flags you want.
Another option is to cut-n-paste the original configure invocation out of the top of config.log and edit it.
I have several compilers with the same name but of different versions or location.
The ./configure script seems to stop at the first it finds in PATH. How can I tell Automake to choose one of them according to a custom rule ? I already have a macro which can check the compiler version.
I would like to avoid setting the path by hand (with the FC variable) as it can be cumbersome to type each time the whole path.
In my case, several MPI wrapper compilers are located in different directories with the same name (and added to the PATH by the user).
The idea would be to use something like ./configure --with-intel to find and select the IntelMPI compiler.
My solution is to set up CC and other "precious" variables via a shell script, lots of them for cross compilation. So I have a bunch of shell scripts sitting around with contents like:
export CROSS_COMPILE=arm-linux
export CC=${CROSS_COMPILE}-gcc
...
PATH=$PATH:/some/arm/compiler/bin:/some/arm/compiler/usr/bin # for arm compiler tools
export CFLAGS="..."
to set up the configure configuration. So at configure time I do:
source /path/to/configuration/some-arm-compiler.sh
./configure ...
It saves a lot of typing.
EDIT: So it could work for your particular case something like:
mpi-a.sh
export FC=mpif90
PATH=$PATH:/path/to/mpi-a/bin:/path/to/mpi-a/usr/bin
mpi-b.sh
export FC=mpif90
PATH=$PATH:/path/to/mpi-b/bin:/path/to/mpi-b/usr/bin
So for compiling with one of them:
source /path/to/mpi-a.sh
./configure ...
and the other:
source /path/to/mpi-b.sh
./configure ...
My solution : copy the search strategy of configure in a macro, with a custom matching criterion. Parsing PATH is done by setting the IFS variable (which is already defined in configure). In Bash, finding all the executables would be something like :
#!/bin/bash
IFS=":"
exe="mpif90"
for dir in $PATH
do
if test -f "$dir/$exe"; then
custom_test($dir/$exe)
fi
done
Note: This is recommanded in the manual
If you need to check the behavior of a program as well as find out whether it is present, you have to write your own test for it.
I wanted to create a makefile. So I wrote instructions in a notepad file.
But what extension should I give while saving this file?
If you run:
make
this program will look for a file named makefile in your directory, and then execute it.
If you have several makefiles, then you can execute them with the command:
make -f MyMakefile
By default, The GNU Make tries some particular names, no using any extension. You can specify file with any name to it. But if you want syntax highlighting in some editors, you can use an extension.
There is a wildcard rule for recognizing make files in Geany editor:
Make=*.mak;*.mk;GNUmakefile;makefile;Makefile;makefile.*;Makefile.*;
From the GNU Make documentation
By default, when make looks for the
makefile, it tries the following
names, in order: GNUmakefile, makefile
and Makefile. Normally you should call
your makefile either makefile or
Makefile
These will be searched for if you don't specify the makefile with the -f flag (Only GNU make will look for GNUMakefile, so give it that name only if you know you're using GNU tools)
It sounds like you're running Windows, in which case makefiles often have a .NMK suffix (because they are intended for use with NMAKE). In the civilised world though makefiles do not generally have a suffix: makefile or Makefile are the canonical file names.
If you need to distinguish one from another, and you are configuration managing the makefile, you should use project.make as the name. On the basis that most LSE's , in particular gedit, are recognising this over .mak. Upon packaging, or sign out to a dedicated folder it can be renamed to makefile, the fully qualified path being descriptive of the project. In this way you can have different versions. If your work is complex enough to be using a makefile you should not mixing multiple builds in the same folder anyway.