VHDL FSM Implementation using port mapping - vhdl

Question

I'm trying to implement VHDL code using Finite state machine and Port mapping to components
Does any one have an idea how to do it, since it isn't allowed to include the port mapping inside the process statement?
------ and_2.vhd (component): ---------
LIBRARY ieee;
USE ieee.std_logic_1164.all;
---------------------------------------
ENTITY and_2 IS
PORT ( a, b: IN STD_LOGIC;
y:OUT STD_LOGIC);
END and_2;
---------------------------------------
ARCHITECTURE and_2 OF and_2 IS
BEGIN
y <= a AND b;
END and_2;
---------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE work.my_data.all;
ENTITY FSM_PORTMAPP IS
PORT(
clk,reset : IN STD_LOGIC;
A,b,c,d: IN STD_LOGIC;
x: out STD_LOGIC
);
END FSM_PORTMAPP;
ARCHITECTURE Flow OF FSM_PORTMAPP IS
-----------------------
COMPONENT and_2 IS
PORT ( a, b: IN STD_LOGIC; y: OUT STD_LOGIC);
END COMPONENT;
-----------------------
TYPE state IS (state0, state1, state2);
SIGNAL pr_state, nx_state: state;
signal y,z :std_logic;
BEGIN
U1:and_2 PORT MAP(a,b ,y);
U2:and_2 PORT MAP(c,d,z);
U3:and_2 PORT MAP(y,z,x);
process(clk,reset)
BEGIN
IF (reset='1') THEN
pr_state <= state0;
ELSIF (clk'EVENT AND clk='1') THEN
pr_state <= nx_state;
END IF;
end process;
process(pr_state)
BEGIN
case pr_state IS
WHEN state0 =>
nx_state <= state1;
WHEN state1=>
nx_state <= state2;
WHEN state2 =>
nx_state <= state0;
END CASE;
end process;
END Flow;
-------------------------------------------------
That is an example for declaration, I want to implement three states, with each state implementing one component.

Answer 1

First of all, think of component instantiation and port mapping as wiring circuit components, not performing operations. The mapping itself does not perform any operation - the logic in the component combined with the signals driven into the component achieve that. This is also why you can't map a component in a process - wiring is a fixed connection, not something that you can perform as a runtime operation. It's not executed code - it's concurrent logic.
In your example code, there are three instances of the component and_2, outside of any process. This mapping is basically what you need (provided you change the component and signal types to your particular function). Then, in your state machine, you can drive the inputs selectively, or read the outputs, or whatever you need. You will probably need some intermediate signals, and you would need to change your wiring around, and what you will most likely get on your first attempt is problematic code with latches where you don't want them and nice things like that. What you can do instead is just register the adder outputs:
U1 : adder_2 port map (a, b, y);
U2 : adder_2 port map (c, d, z);
U3 : adder_2 port map (y_r, z_r, x);
adder_regs : process (clk)
begin
if rising_edge(clk) then
y_r <= y;
z_r <= z;
end if;
end process adder_regs;
Or is there some other reason you're trying to do it the way you are?