I am using a makefile to control the compilation of my project. At the start of my Makefile, I have:
ifdef PIXEL
CFLAGS += -DBY_PIXEL
else
ifdef LINE
CFLAGS += -DBY_LINE
else
ifdef BLOCK
CFLAGS += -DBY_BLOCK
else
CFLAGS += -DBY_PIXEL (HERE)
endif
endif
endif
I have the error "No rule to make target XXX" where XXX is PIXEL, LINE or BLOCK. However when I don't write any parameter, it finds the target in the last else (where I put (HERE).
I dont fully understand why but I don't often write Makefile. Do you guys have an idea about it?
To specify a variable for make, set it to a value after the make command. For example, make PIXEL=foo build
Related
I have a makefile that looks something like this:
include anotherFile.mk
all:
someStuff
The file anotherFile.mk is like this:
include yetAnotherFile.mk
export SOME_VAR = 93
The problem is that anotherFile.mk and yetAnotherFile.mk are in a different directory from my Makefile. So my makefile can't just be changed to this:
include $(OTHER_PROJECT_PATH)/anotherFile.mk
all:
someStuff
The problem with this approach is that the include statement in anotherFile.mk will fail because it will be searching in the current directory.
A partial solution that I found is to pass the --include-dir=$OTHER_PROJECT_PATH flag to the invocation of make, but that's a bit user-unfriendly.
So my question is: Is there something I can put inside my makefile that will add to the directories that make searches for when executing an include? Something like MAKE_INCLUDE_DIRS += $(OTHER_PROJECT_PATH)
Surprisingly there doesn't seem to be a good answer to that question. Forcing .INCLUDE_DIR doesn't help and there doesn't seem to be any way around invoking make with --include-dir=$OTHER_PROJECT_PATH.
It is however possible to put the appropriate recursive make invocation inside the makefile but, in order to get it to work for all reasonable cases it quickly becomes too complicated to be worth it. In summary it requires:
a top level condition to check if the OTHER_PROJECT_PATH is in .INCLUDE_DIR
the appropriate target with the recipe invoking make recursively
possibly additional targets if there are multiple command goals
the real make file enclosed in the else part of the conditional
You Makefile would look like this:
OTHER_PROJECT_PATH := other
ifeq (,$(filter $(OTHER_PROJECT_PATH), $(.INCLUDE_DIRS)))
# this is the mechanism to add the include dir in a recursive make
$(or $(firstword $(MAKECMDGOALS)),all):
$(MAKE) -I$(OTHER_PROJECT_PATH) $(MAKECMDGOALS)
# add empty targets for additional goals if needed
ifneq (,$(wordlist 2,$(words $(MAKECMDGOALS)),$(MAKECMDGOALS)))
$(wordlist 2,$(words $(MAKECMDGOALS)),$(MAKECMDGOALS)):
endif
else
# this is where the real makefile starts
all more:
echo $#: $< $^
include a.mak
endif
It still does not seem possible from a makefile, but if you have a script that sets up environment variables, you can use MAKEFLAGS (e.g. export MAKEFLAGS=I/your/path ordentlich on Linux, or SET on Windows)
Is there any GNU Make special variable for knowing which target was the one sent by the user in the command line call? To achieve something like (it is just an example):
// makefile
ifeq ($(USER_TARGET),"plain")
CXXFLAGS += -O0
else
CXXFLAGS += -O3
endif
plain:
// do something using CXXFLAGS
all:
// other rule using CXXFLAGS
It's important that, the USER_TARGET variable (which can be an special GNU Make variable, or a custom variable which value was set by some special GNU Make function returning the user target), contains the original target specified by the user in a call like:
$ make plain
and not the value in any step of the dependency tree. In other words, the USER_TARGET must not change during the building dependence chain, because, if I'm not wrong, the value of USER_TARGET will be evaluated when it is used by the first time, and than can happen in any point of the document, so, I want to be sure the current step of building chain don't change the value of USER_TARGET.
I don't know if I have been clear enough or if it is was overexplained.
If there is no built-in mechanism for that in GNU Make, any $(shell command) trick is welcome as well.
You want the MAKECMDGOALS variable, described here.
I have attached the sample of the make file.
# SELECT TARGET OPERATING SYSTEM
override OS = LINUX
#OS = WINDOWS
CC = gcc
SRC_DIR = src
INC_DIR = inc
OBJ_DIR = obj
CFLAGS = -c -Wall -I$(INC_DIR)
# CONDITIONAL COMPILATION
ifeq ($(OS), "WINDOWS")
SERIAL = Winsrcfile
CLEAR = cls
endif
ifeq ($(OS), "LINUX")
SERIAL = Linsrcfile
CLEAR = clear
endif
I am trying to achieve this...
make OS=WINDOWS // compile for windows
or
make OS=LINUX // compile for linux
from linux shell or windows command prompt and want default to be linux, if OS is not specified while executing 'make'. But the ifeq returns false in both cases, generating an error 'No rule to make target'. I read override directive & conditional syntax but it seems i havent got a clear idea of it. I have tried every alternate syntax of conditional syntax. But get error 'invalid syntax in conditional. Stop'
Make doesn't distinguish quotation marks. What you should do instead is:
ifeq ($(OS),LINUX)
# do stuff
endif
What's actually done here is that the arguments are expanded and then compared literally. $(OS) expands to the value of the variable and LINUX expands to LINUX. Your example would for example require make OS='"Linux"' in order to work
I am using makefile to build my program in multiple system. Some system have installed colorgcc script. In my Makefile i want to check, if script exists
and depending on it i setting up CC variable. But my Makefile don't work correctly - in system, that haven't colorgcc, make always set $(CC) as colorgcc. Here's part of Makefile:
ifneq ("$(wildchar /usr/bin/colorgcc)","")
CC=colorgcc
else
CC=gcc
endif
I also tried to use this variant:
ifeq ( $(shell test -e /usr/bin/colorgcc), )
CC=colorgcc
else
CC=gcc
endif
In both case $(CC) doesn't depend of existence file /usr/bin/colorgcc
How can i solve my problem?
In the first case, you mistyped the function $(wildcard ...) so you get nothing, always.
In the second case, the output of test is always the empty string. It will set its exit code depending on whether the condition is true or not, but you are not examining its exit code, just the output it prints, which will always be nothing at all.
I am trying to build a shared library with one set of code, and everything works, except for this issue with my Makefile. Here's my (simplified) Makefile thus far:
OBJS = bar.o
libfoo.so: OS = LINUX # These don't seem to happen
libfoo.dll: OS = WINDOWS
# Linux
ifeq ($(OS), LINUX)
CC = gcc
...
# Windows
else ifeq ($(OS), WINDOWS)
CC = i686-pc-mingw32-gcc
...
endif
all: libfoo.so libfoo.dll
libfoo.so: clean $(OBJS)
...
libfoo.dll: clean $(OBJS)
...
bar.o: bar_$(OS).c bar.h
...
So, when you type make libfoo.so, I expect it to set OS = LINUX first. Then, when it gets to bar.o (it is a dependency of libfoo) it should know which bar_$(OS).c to use. However, I get the error:
make: *** No rule to make target `bar_.c', needed by bar.o. Stop.
Which tells me that when it tries to make bar.o, $(OS) is not set. But shouldn't that be the first thing that happens when I try to make libfoo.so, and that rule is evaluated?
Target-specific variables are available in the body of the rule, not in its prerequisites. But even if you could get this to work, you'd be asking for trouble: if you build one library and then the other, there's no way for Make to know that the bar.o that was made for the first is wrong for the second and should not be used.
There are several ways to get the effect you want, but none is perfect. I'd suggest using two different object file names, like bar_unix.o and bar_windows.o.
If you want to set a target-specific variable, and then have that variable available outside the body of that rule, you can recursively call the Makefile, after exporting the variable:
OBJS ?= foo.o # Use ? so it isn't blown away on recursive call
libfoo.so: OS = LINUX
libfoo.so: OBJS += linux_only.o
libfoo.so:
$(MAKE) -s build_libfoo_linux
build_libfoo_linux: $(OBJS)
#echo "OS = $(OS)" # Should print "OS = LINUX"
export OS # Can be anywhere
You have to remember to export the variables you want to "persist" after the recursive make call. And also, as shown above, if you append to any variables before the call, you'll want to make their initial assignment with ?= so they aren't set the second time.
You might want to detect the OS using uname and then conditionally compile. This explains