Could anyone please tell me about the AXI bus and its signals. I would also want to know about AXI bus to wishbone bus wrapper to implement it in VHDL.
I am looking at the implementation of a register in FPGA and then give the corresponding commands from LINUX to drive the LED's on a zedboard. wishbone bus is used to transfer the data and make communication with the register.
Here are some documents for the AMBA (Advanced Microcontroller Bus Architecture) including AXI and AXI-Light:
Xilinx UG761 - AXI Reference Guide
ARM - AMBA Open Specifications
Wikipedia article
If you are going to write a GPIO to register mapping module for WishBone, why don't you write a AXI to register / GPIO mapper and spare the AXI2WB bridge?
I thought OpenCores has a AXI2WB wrapper, but I can't find it.
I know, that this is an old question, but as there is no answer providing link to the right HDL source, I'd like to propose a few:
There is an AXI to WB bridge written in Verilog by Daniel Strother (it was written in 2011)
On OpenCores there is a very simple AXI4-Lite to Wishbone bridge (the project contains also AXI4-Lite to IPbus bridge) written in VHDL by me and my colleague.
Related
I am testing a custom FPGA NIC and I need to send management information (such as header info for matching) and traffic data to it using a traffic generator from within the user space.
The driver built for the FPGA is a modified version of IXGBE with DMA support for management, and also supports DPDK for kernel bypass to achieve high throughput.
I am trying to understand how the various software (driver, userspace application, etc) should be stacked/connected to each-other so I can achieve the objective of reading and writing to PCIe on the NIC using set of scripts from user space?
I have also been looking at this project
https://github.com/CospanDesign/python-pci
which is useful however based on Xilinx XDMA.
Would appreciate any help, pointers on this.
Sorry, the question is too broad. For such a broad question there is a generic answer: have a look at Inter Process Communication:
https://en.wikipedia.org/wiki/Inter-process_communication
There are variety of methods, like Unix sockets, shared memory, netlink etc, to communicate between user space processes. As well as a variety of methods to communicate between user space and kernel space.
Just pick the best for you and try to do something. If it fails, come again on SO and ask ;)
I am looking to transfer data from the zynq ddr to a custom ip, then store the result on the sd card. The sd card is connected through the emio pin, so it is available to the PL. So far, I can access the DDR from Windows, so I put files there. All I need is to connect each component in vhdl to send and receive data from each other. My current Block diagram has AXI stream FIFo, AXI DMA, BRAM generator, and BRAM controller. I've read different tutorials, and only find how to set up the hardware, but not how to connect each piece. Any ideas?
Block Design
The easiest way is using a Linux distro to access the SD card.
Afterwards you can use AXI4 or AXI4S to communicate.
DMA is you friend to copy data from RAM to AXIS and back.
If you want to transfer data directly using AXI4 you can test it with devmem from busybox by accessing the corresponding register. This can be AXI BRAM Controller or AXI GPIO for example.
I am using a i.Mx6 Sabre Lite board running Linux Kernel 3.14.18 and board is supposed to act as a USB Device (USB Gadget). One Vendor specific interface need to be added into CDC/NCM Configuration. CDC/NCM Configuration by default has two standard interfaces - Communication & Data. I have added third interface (Vendor specific) to CDC/NCM Configuration. This interface has two Bulk (IN & OUT) Endpoints. I can verify this newly added interface once board is connected to PC using "lsusb".
Problem:
I cannot see the newly added interface getting exposed to user-space on i.Mx Board or PC, like standard NCM interfaces can be seen as usb0 (Ethernet device) on i.Mx Board as well as on PC and I can PING to/from board using usb0.
If I have to hookup this newly added interface with some g_"driver" (just like standard NCM interfaces are hooked to g_ether); then what is the best choice for BULK I/O?
How to make this newly added vendor specific interface available to i.MX6 user space so as to do read/write on it from Linux Application? I came to know about GadgetFS; but any example would be
Hope someone must have tried similar thing in Linux-USB and can guide.
A vendor-specific interface does not use a standard protocol, so it is not possible to use one of the standard drivers. (And bulk is not a protocol, it is a mechanism to implement your own protocol.)
To access such an interface, you have to use the low-level functions from something like libusb.
I have a project that I need to control my Irobot creative using microblaze and Pmodacl or Pmodjstck from digilent.
I already set up my peripheral to be SPI interface (I also understand SPI working); however, I dont know how to communicate with the pmodacl?
I have searched all over the net and I dont see any example how to do it. I would be a great help if you give me some example.
Is there any AXI4Lite slave IP (Verilog, VHDL) available under GNU GPL?
I want to test a virtual AXI4 master in a uP system and hence this requirement.
Just an AXI4 slave or AXI3 slave will also do (I can strip down the signals to make it AXI4Lite compatible).
Any links, source code will be helpful.
You can use AXI slave template implemented in the following repository (VHDL, BSD license):
https://github.com/sergeykhbr/riscv_vhdl
File types_nasti.vhd implements general methods to work with the AXI bus. NASTI is the other name of the AXI interface invented by this team
http://riscv.org to avoid trademark usage problems.
The project structure is very similiar to Gailser's LEON3 implementation but it implements 64-bits Rocket-Chip CPU (RISC-V ISA) and several AXI4 modules: UART, GPIO, IRQ controller etc.
A clear idea about AXI protocol can be obtained at AMBA AXI and ACE Protocol Specification AXI3, AXI4, and ....
Other opencore small purpose IP is available at opencore website.
Many YouTube videos are also helpful for beginners. video site.
A detailed understanding about AXI IP is a must thing for designing it.