I have a project that I need to control my Irobot creative using microblaze and Pmodacl or Pmodjstck from digilent.
I already set up my peripheral to be SPI interface (I also understand SPI working); however, I dont know how to communicate with the pmodacl?
I have searched all over the net and I dont see any example how to do it. I would be a great help if you give me some example.
Related
im working on a kernel driver for the Texas instruments tps92518-Q1 and tps92518HV-Q1
an am unsure of the "correct" way to register the regulator
so far I've found three possibilities
regulator_register() from /drivers/regulator/core.c
devm_regulator_register() from /drivers/regulator/devres.c
platform_device_register() from /drivers/base/platform.c
regulator_register() is described in kernel docs regulator api reference but is only used by two drivers
devm_regulator_register() is used by various existing drivers
platform_device_register() is described in linux/Documentation/power/regulator/machine.rst but only seem to be used in one driver
I am testing a custom FPGA NIC and I need to send management information (such as header info for matching) and traffic data to it using a traffic generator from within the user space.
The driver built for the FPGA is a modified version of IXGBE with DMA support for management, and also supports DPDK for kernel bypass to achieve high throughput.
I am trying to understand how the various software (driver, userspace application, etc) should be stacked/connected to each-other so I can achieve the objective of reading and writing to PCIe on the NIC using set of scripts from user space?
I have also been looking at this project
https://github.com/CospanDesign/python-pci
which is useful however based on Xilinx XDMA.
Would appreciate any help, pointers on this.
Sorry, the question is too broad. For such a broad question there is a generic answer: have a look at Inter Process Communication:
https://en.wikipedia.org/wiki/Inter-process_communication
There are variety of methods, like Unix sockets, shared memory, netlink etc, to communicate between user space processes. As well as a variety of methods to communicate between user space and kernel space.
Just pick the best for you and try to do something. If it fails, come again on SO and ask ;)
Is there any AXI4Lite slave IP (Verilog, VHDL) available under GNU GPL?
I want to test a virtual AXI4 master in a uP system and hence this requirement.
Just an AXI4 slave or AXI3 slave will also do (I can strip down the signals to make it AXI4Lite compatible).
Any links, source code will be helpful.
You can use AXI slave template implemented in the following repository (VHDL, BSD license):
https://github.com/sergeykhbr/riscv_vhdl
File types_nasti.vhd implements general methods to work with the AXI bus. NASTI is the other name of the AXI interface invented by this team
http://riscv.org to avoid trademark usage problems.
The project structure is very similiar to Gailser's LEON3 implementation but it implements 64-bits Rocket-Chip CPU (RISC-V ISA) and several AXI4 modules: UART, GPIO, IRQ controller etc.
A clear idea about AXI protocol can be obtained at AMBA AXI and ACE Protocol Specification AXI3, AXI4, and ....
Other opencore small purpose IP is available at opencore website.
Many YouTube videos are also helpful for beginners. video site.
A detailed understanding about AXI IP is a must thing for designing it.
Could anyone please tell me about the AXI bus and its signals. I would also want to know about AXI bus to wishbone bus wrapper to implement it in VHDL.
I am looking at the implementation of a register in FPGA and then give the corresponding commands from LINUX to drive the LED's on a zedboard. wishbone bus is used to transfer the data and make communication with the register.
Here are some documents for the AMBA (Advanced Microcontroller Bus Architecture) including AXI and AXI-Light:
Xilinx UG761 - AXI Reference Guide
ARM - AMBA Open Specifications
Wikipedia article
If you are going to write a GPIO to register mapping module for WishBone, why don't you write a AXI to register / GPIO mapper and spare the AXI2WB bridge?
I thought OpenCores has a AXI2WB wrapper, but I can't find it.
I know, that this is an old question, but as there is no answer providing link to the right HDL source, I'd like to propose a few:
There is an AXI to WB bridge written in Verilog by Daniel Strother (it was written in 2011)
On OpenCores there is a very simple AXI4-Lite to Wishbone bridge (the project contains also AXI4-Lite to IPbus bridge) written in VHDL by me and my colleague.
WHat I only need is to be able to read/write to the slave registers of my custom IP and be able send a software reset and give clock to my custom IP module. What can I exclude from the bus signals so to be able to insert more ports for my custom IP, in overcoming the limitation of the IOBs.
Honestly, you can't leave out anything. There's a very good reason it's called a bus standard.
Write you logic in Verilog or VHDL and then just use the EDK import peripheral tool and you're done.
Make your peripheral as simple as you want/need it. The tool will properly wrap it in the bus logic and provide the necessary files for the /data directory of your pcore.
All the seeminly "extra" connections really don't cost you any chip-area or performance. But leave the wrong thing out and you'll spend weeks trying to sort out the mess.