Serial fir filter in VHDL - filter
I want to do a serial fir filter with LUT table. Here is my code:
Register module
library ieee;
use ieee.std_logic_1164.all;
entity reg is
port(
clk, rst : in std_logic;
d : in std_logic_vector(13 downto 0);
q : out std_logic_vector(13 downto 0)
);
end reg;
architecture arch of reg is
signal q_reg, q_next : std_logic_vector(13 downto 0);
begin
process(clk, rst)
begin
if (rst ='1') then
q_reg <= (others => '0');
elsif rising_edge(clk) then
q_reg <= q_next;
end if;
end process;
q_next <= d;
q <= q_reg;
end arch;
Adder module:
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity add is
port (
a,b : in std_logic_vector(13 downto 0);
s : out std_logic_vector(13 downto 0)
);
end add;
architecture arch of add is
signal result : signed(13 downto 0);
begin
result <= signed(a) + signed(b);
s <= std_logic_vector(result);
end arch;
Lut table:
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
entity lut_table is
port(
table_in : in std_logic_vector(8 downto 0);
table_out : out std_logic_vector(13 downto 0)
);
end lut_table;
architecture arch of lut_table is
begin
with table_in select
table_out <= "00000000000000" when "000000000",
"00000001101110" when "000000001",
"11111110111011" when "000000010",
"00000000101001" when "000000011",
"00000101000000" when "000000100",
"00000110101110" when "000000101",
"00000011111011" when "000000110",
"00000101101001" when "000000111",
"00010001000101" when "000001000",
"00010010110011" when "000001001",
"00010000000000" when "000001010",
"00010001101110" when "000001011",
"00010110000101" when "000001100",
"00010111110011" when "000001101",
"00010101000000" when "000001110",
"00010110101110" when "000001111",
"00100110100110" when "000010000",
"00101000010100" when "000010001",
"00100101100001" when "000010010",
"00100111001111" when "000010011",
"00101011100110" when "000010100",
"00101101010100" when "000010101",
"00101010100001" when "000010110",
"00101100001111" when "000010111",
"00110111101011" when "000011000",
"00111001011001" when "000011001",
"00110110100110" when "000011010",
"00111000010100" when "000011011",
"00111100101011" when "000011100",
"00111110011001" when "000011101",
"00111011100110" when "000011110",
"00111101010100" when "000011111",
"00010001000101" when "000100000",
"00010010110011" when "000100001",
"00010000000000" when "000100010",
"00010001101110" when "000100011",
"00010110000101" when "000100100",
"00010111110011" when "000100101",
"00010101000000" when "000100110",
"00010110101110" when "000100111",
"00100010001010" when "000101000",
"00100011111000" when "000101001",
"00100001000101" when "000101010",
"00100010110011" when "000101011",
"00100111001010" when "000101100",
"00101000111000" when "000101101",
"00100110000101" when "000101110",
"00100111110011" when "000101111",
"00110111101011" when "000110000",
"00111001011001" when "000110001",
"00110110100110" when "000110010",
"00111000010100" when "000110011",
"00111100101011" when "000110100",
"00111110011001" when "000110101",
"00111011100110" when "000110110",
"00111101010100" when "000110111",
"01001000110000" when "000111000",
"01001010011110" when "000111001",
"01000111101011" when "000111010",
"01001001011001" when "000111011",
"01001101110000" when "000111100",
"01001111011110" when "000111101",
"01001100101011" when "000111110",
"01001110011001" when "000111111",
"00000101000000" when "001000000",
"00000110101110" when "001000001",
"00000011111011" when "001000010",
"00000101101001" when "001000011",
"00001010000000" when "001000100",
"00001011101110" when "001000101",
"00001000111011" when "001000110",
"00001010101001" when "001000111",
"00010110000101" when "001001000",
"00010111110011" when "001001001",
"00010101000000" when "001001010",
"00010110101110" when "001001011",
"00011011000101" when "001001100",
"00011100110011" when "001001101",
"00011010000000" when "001001110",
"00011011101110" when "001001111",
"00101011100110" when "001010000",
"00101101010100" when "001010001",
"00101010100001" when "001010010",
"00101100001111" when "001010011",
"00110000100110" when "001010100",
"00110010010100" when "001010101",
"00101111100001" when "001010110",
"00110001001111" when "001010111",
"00111100101011" when "001011000",
"00111110011001" when "001011001",
"00111011100110" when "001011010",
"00111101010100" when "001011011",
"01000001101011" when "001011100",
"01000011011001" when "001011101",
"01000000100110" when "001011110",
"01000010010100" when "001011111",
"00010110000101" when "001100000",
"00010111110011" when "001100001",
"00010101000000" when "001100010",
"00010110101110" when "001100011",
"00011011000101" when "001100100",
"00011100110011" when "001100101",
"00011010000000" when "001100110",
"00011011101110" when "001100111",
"00100111001010" when "001101000",
"00101000111000" when "001101001",
"00100110000101" when "001101010",
"00100111110011" when "001101011",
"00101100001010" when "001101100",
"00101101111000" when "001101101",
"00101011000101" when "001101110",
"00101100110011" when "001101111",
"00111100101011" when "001110000",
"00111110011001" when "001110001",
"00111011100110" when "001110010",
"00111101010100" when "001110011",
"01000001101011" when "001110100",
"01000011011001" when "001110101",
"01000000100110" when "001110110",
"01000010010100" when "001110111",
"01001101110000" when "001111000",
"01001111011110" when "001111001",
"01001100101011" when "001111010",
"01001110011001" when "001111011",
"01010010110000" when "001111100",
"01010100011110" when "001111101",
"01010001101011" when "001111110",
"01010011011001" when "001111111",
"11111110111011" when "010000000",
"00000000101001" when "010000001",
"11111101110110" when "010000010",
"11111111100100" when "010000011",
"00000011111011" when "010000100",
"00000101101001" when "010000101",
"00000010110110" when "010000110",
"00000100100100" when "010000111",
"00010000000000" when "010001000",
"00010001101110" when "010001001",
"00001110111011" when "010001010",
"00010000101001" when "010001011",
"00010101000000" when "010001100",
"00010110101110" when "010001101",
"00010011111011" when "010001110",
"00010101101001" when "010001111",
"00100101100001" when "010010000",
"00100111001111" when "010010001",
"00100100011100" when "010010010",
"00100110001010" when "010010011",
"00101010100001" when "010010100",
"00101100001111" when "010010101",
"00101001011100" when "010010110",
"00101011001010" when "010010111",
"00110110100110" when "010011000",
"00111000010100" when "010011001",
"00110101100001" when "010011010",
"00110111001111" when "010011011",
"00111011100110" when "010011100",
"00111101010100" when "010011101",
"00111010100001" when "010011110",
"00111100001111" when "010011111",
"00010000000000" when "010100000",
"00010001101110" when "010100001",
"00001110111011" when "010100010",
"00010000101001" when "010100011",
"00010101000000" when "010100100",
"00010110101110" when "010100101",
"00010011111011" when "010100110",
"00010101101001" when "010100111",
"00100001000101" when "010101000",
"00100010110011" when "010101001",
"00100000000000" when "010101010",
"00100001101110" when "010101011",
"00100110000101" when "010101100",
"00100111110011" when "010101101",
"00100101000000" when "010101110",
"00100110101110" when "010101111",
"00110110100110" when "010110000",
"00111000010100" when "010110001",
"00110101100001" when "010110010",
"00110111001111" when "010110011",
"00111011100110" when "010110100",
"00111101010100" when "010110101",
"00111010100001" when "010110110",
"00111100001111" when "010110111",
"01000111101011" when "010111000",
"01001001011001" when "010111001",
"01000110100110" when "010111010",
"01001000010100" when "010111011",
"01001100101011" when "010111100",
"01001110011001" when "010111101",
"01001011100110" when "010111110",
"01001101010100" when "010111111",
"00000011111011" when "011000000",
"00000101101001" when "011000001",
"00000010110110" when "011000010",
"00000100100100" when "011000011",
"00001000111011" when "011000100",
"00001010101001" when "011000101",
"00000111110110" when "011000110",
"00001001100100" when "011000111",
"00010101000000" when "011001000",
"00010110101110" when "011001001",
"00010011111011" when "011001010",
"00010101101001" when "011001011",
"00011010000000" when "011001100",
"00011011101110" when "011001101",
"00011000111011" when "011001110",
"00011010101001" when "011001111",
"00101010100001" when "011010000",
"00101100001111" when "011010001",
"00101001011100" when "011010010",
"00101011001010" when "011010011",
"00101111100001" when "011010100",
"00110001001111" when "011010101",
"00101110011100" when "011010110",
"00110000001010" when "011010111",
"00111011100110" when "011011000",
"00111101010100" when "011011001",
"00111010100001" when "011011010",
"00111100001111" when "011011011",
"01000000100110" when "011011100",
"01000010010100" when "011011101",
"00111111100001" when "011011110",
"01000001001111" when "011011111",
"00010101000000" when "011100000",
"00010110101110" when "011100001",
"00010011111011" when "011100010",
"00010101101001" when "011100011",
"00011010000000" when "011100100",
"00011011101110" when "011100101",
"00011000111011" when "011100110",
"00011010101001" when "011100111",
"00100110000101" when "011101000",
"00100111110011" when "011101001",
"00100101000000" when "011101010",
"00100110101110" when "011101011",
"00101011000101" when "011101100",
"00101100110011" when "011101101",
"00101010000000" when "011101110",
"00101011101110" when "011101111",
"00111011100110" when "011110000",
"00111101010100" when "011110001",
"00111010100001" when "011110010",
"00111100001111" when "011110011",
"01000000100110" when "011110100",
"01000010010100" when "011110101",
"00111111100001" when "011110110",
"01000001001111" when "011110111",
"01001100101011" when "011111000",
"01001110011001" when "011111001",
"01001011100110" when "011111010",
"01001101010100" when "011111011",
"01010001101011" when "011111100",
"01010011011001" when "011111101",
"01010000100110" when "011111110",
"01010010010100" when "011111111",
"00000001101110" when "100000000",
"00000011011100" when "100000001",
"00000000101001" when "100000010",
"00000010010111" when "100000011",
"00000110101110" when "100000100",
"00001000011100" when "100000101",
"00000101101001" when "100000110",
"00000111010111" when "100000111",
"00010010110011" when "100001000",
"00010100100001" when "100001001",
"00010001101110" when "100001010",
"00010011011100" when "100001011",
"00010111110011" when "100001100",
"00011001100001" when "100001101",
"00010110101110" when "100001110",
"00011000011100" when "100001111",
"00101000010100" when "100010000",
"00101010000010" when "100010001",
"00100111001111" when "100010010",
"00101000111101" when "100010011",
"00101101010100" when "100010100",
"00101111000010" when "100010101",
"00101100001111" when "100010110",
"00101101111101" when "100010111",
"00111001011001" when "100011000",
"00111011000111" when "100011001",
"00111000010100" when "100011010",
"00111010000010" when "100011011",
"00111110011001" when "100011100",
"01000000000111" when "100011101",
"00111101010100" when "100011110",
"00111111000010" when "100011111",
"00010010110011" when "100100000",
"00010100100001" when "100100001",
"00010001101110" when "100100010",
"00010011011100" when "100100011",
"00010111110011" when "100100100",
"00011001100001" when "100100101",
"00010110101110" when "100100110",
"00011000011100" when "100100111",
"00100011111000" when "100101000",
"00100101100110" when "100101001",
"00100010110011" when "100101010",
"00100100100001" when "100101011",
"00101000111000" when "100101100",
"00101010100110" when "100101101",
"00100111110011" when "100101110",
"00101001100001" when "100101111",
"00111001011001" when "100110000",
"00111011000111" when "100110001",
"00111000010100" when "100110010",
"00111010000010" when "100110011",
"00111110011001" when "100110100",
"01000000000111" when "100110101",
"00111101010100" when "100110110",
"00111111000010" when "100110111",
"01001010011110" when "100111000",
"01001100001100" when "100111001",
"01001001011001" when "100111010",
"01001011000111" when "100111011",
"01001111011110" when "100111100",
"01010001001100" when "100111101",
"01001110011001" when "100111110",
"01010000000111" when "100111111",
"00000110101110" when "101000000",
"00001000011100" when "101000001",
"00000101101001" when "101000010",
"00000111010111" when "101000011",
"00001011101110" when "101000100",
"00001101011100" when "101000101",
"00001010101001" when "101000110",
"00001100010111" when "101000111",
"00010111110011" when "101001000",
"00011001100001" when "101001001",
"00010110101110" when "101001010",
"00011000011100" when "101001011",
"00011100110011" when "101001100",
"00011110100001" when "101001101",
"00011011101110" when "101001110",
"00011101011100" when "101001111",
"00101101010100" when "101010000",
"00101111000010" when "101010001",
"00101100001111" when "101010010",
"00101101111101" when "101010011",
"00110010010100" when "101010100",
"00110100000010" when "101010101",
"00110001001111" when "101010110",
"00110010111101" when "101010111",
"00111110011001" when "101011000",
"01000000000111" when "101011001",
"00111101010100" when "101011010",
"00111111000010" when "101011011",
"01000011011001" when "101011100",
"01000101000111" when "101011101",
"01000010010100" when "101011110",
"01000100000010" when "101011111",
"00010111110011" when "101100000",
"00011001100001" when "101100001",
"00010110101110" when "101100010",
"00011000011100" when "101100011",
"00011100110011" when "101100100",
"00011110100001" when "101100101",
"00011011101110" when "101100110",
"00011101011100" when "101100111",
"00101000111000" when "101101000",
"00101010100110" when "101101001",
"00100111110011" when "101101010",
"00101001100001" when "101101011",
"00101101111000" when "101101100",
"00101111100110" when "101101101",
"00101100110011" when "101101110",
"00101110100001" when "101101111",
"00111110011001" when "101110000",
"01000000000111" when "101110001",
"00111101010100" when "101110010",
"00111111000010" when "101110011",
"01000011011001" when "101110100",
"01000101000111" when "101110101",
"01000010010100" when "101110110",
"01000100000010" when "101110111",
"01001111011110" when "101111000",
"01010001001100" when "101111001",
"01001110011001" when "101111010",
"01010000000111" when "101111011",
"01010100011110" when "101111100",
"01010110001100" when "101111101",
"01010011011001" when "101111110",
"01010101000111" when "101111111",
"00000000101001" when "110000000",
"00000010010111" when "110000001",
"11111111100100" when "110000010",
"00000001010010" when "110000011",
"00000101101001" when "110000100",
"00000111010111" when "110000101",
"00000100100100" when "110000110",
"00000110010010" when "110000111",
"00010001101110" when "110001000",
"00010011011100" when "110001001",
"00010000101001" when "110001010",
"00010010010111" when "110001011",
"00010110101110" when "110001100",
"00011000011100" when "110001101",
"00010101101001" when "110001110",
"00010111010111" when "110001111",
"00100111001111" when "110010000",
"00101000111101" when "110010001",
"00100110001010" when "110010010",
"00100111111000" when "110010011",
"00101100001111" when "110010100",
"00101101111101" when "110010101",
"00101011001010" when "110010110",
"00101100111000" when "110010111",
"00111000010100" when "110011000",
"00111010000010" when "110011001",
"00110111001111" when "110011010",
"00111000111101" when "110011011",
"00111101010100" when "110011100",
"00111111000010" when "110011101",
"00111100001111" when "110011110",
"00111101111101" when "110011111",
"00010001101110" when "110100000",
"00010011011100" when "110100001",
"00010000101001" when "110100010",
"00010010010111" when "110100011",
"00010110101110" when "110100100",
"00011000011100" when "110100101",
"00010101101001" when "110100110",
"00010111010111" when "110100111",
"00100010110011" when "110101000",
"00100100100001" when "110101001",
"00100001101110" when "110101010",
"00100011011100" when "110101011",
"00100111110011" when "110101100",
"00101001100001" when "110101101",
"00100110101110" when "110101110",
"00101000011100" when "110101111",
"00111000010100" when "110110000",
"00111010000010" when "110110001",
"00110111001111" when "110110010",
"00111000111101" when "110110011",
"00111101010100" when "110110100",
"00111111000010" when "110110101",
"00111100001111" when "110110110",
"00111101111101" when "110110111",
"01001001011001" when "110111000",
"01001011000111" when "110111001",
"01001000010100" when "110111010",
"01001010000010" when "110111011",
"01001110011001" when "110111100",
"01010000000111" when "110111101",
"01001101010100" when "110111110",
"01001111000010" when "110111111",
"00000101101001" when "111000000",
"00000111010111" when "111000001",
"00000100100100" when "111000010",
"00000110010010" when "111000011",
"00001010101001" when "111000100",
"00001100010111" when "111000101",
"00001001100100" when "111000110",
"00001011010010" when "111000111",
"00010110101110" when "111001000",
"00011000011100" when "111001001",
"00010101101001" when "111001010",
"00010111010111" when "111001011",
"00011011101110" when "111001100",
"00011101011100" when "111001101",
"00011010101001" when "111001110",
"00011100010111" when "111001111",
"00101100001111" when "111010000",
"00101101111101" when "111010001",
"00101011001010" when "111010010",
"00101100111000" when "111010011",
"00110001001111" when "111010100",
"00110010111101" when "111010101",
"00110000001010" when "111010110",
"00110001111000" when "111010111",
"00111101010100" when "111011000",
"00111111000010" when "111011001",
"00111100001111" when "111011010",
"00111101111101" when "111011011",
"01000010010100" when "111011100",
"01000100000010" when "111011101",
"01000001001111" when "111011110",
"01000010111101" when "111011111",
"00010110101110" when "111100000",
"00011000011100" when "111100001",
"00010101101001" when "111100010",
"00010111010111" when "111100011",
"00011011101110" when "111100100",
"00011101011100" when "111100101",
"00011010101001" when "111100110",
"00011100010111" when "111100111",
"00100111110011" when "111101000",
"00101001100001" when "111101001",
"00100110101110" when "111101010",
"00101000011100" when "111101011",
"00101100110011" when "111101100",
"00101110100001" when "111101101",
"00101011101110" when "111101110",
"00101101011100" when "111101111",
"00111101010100" when "111110000",
"00111111000010" when "111110001",
"00111100001111" when "111110010",
"00111101111101" when "111110011",
"01000010010100" when "111110100",
"01000100000010" when "111110101",
"01000001001111" when "111110110",
"01000010111101" when "111110111",
"01001110011001" when "111111000",
"01010000000111" when "111111001",
"01001101010100" when "111111010",
"01001111000010" when "111111011",
"01010011011001" when "111111100",
"01010101000111" when "111111101",
"01010010010100" when "111111110",
"01010100000010" when "111111111";
end arch;
Top level entity file:
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity top is
port(
clk, rst : in std_logic;
data_in : in std_logic_vector(7 downto 0);
data_out : out std_logic_vector(13 downto 0);
aaa : out unsigned(3 downto 0);
ena : out std_logic;
data_p : out std_logic_vector(8 downto 0)
);
end top;
architecture arch of top is
signal tablein : std_logic_vector(8 downto 0);
signal tableout: std_logic_vector(13 downto 0);
signal addout,add1,add2 : std_logic_vector(13 downto 0);
signal reg_in, reg_out : std_logic_vector(13 downto 0);
--signal tap0, tap1, tap2, tap3, tap4, tap5, tap6, tap7 : std_logic_vector(8 DOWNTO 0);
signal x0, x1, x2, x3, x4, x5, x6, x7, x8 : std_logic_vector(7 DOWNTO 0);
--signal y0, y1, y2, y3, y4, y5, y6, y7,y8 : std_logic_vector(13 downto 0);
--type TYPEX is array (8 downto 1) of std_logic_vector(8 downto 0);
type TYPET is array (0 to 7) of std_logic_vector(8 downto 0);
signal tap : TYPET;
--signal x : TYPEX;
signal i : unsigned(3 downto 0);
signal enaa : std_logic;
component reg
port(
clk, rst : in std_logic;
d : in std_logic_vector(13 downto 0);
q : out std_logic_vector(13 downto 0)
);
end component;
component add
port(
a,b : in std_logic_vector(13 downto 0);
s : out std_logic_vector(13 downto 0)
);
end component;
component lut_table
port(
table_in : in std_logic_vector(8 downto 0);
table_out : out std_logic_vector(13 downto 0)
);
end component;
begin
a2: add port map (
a => add1,
b => add2,
s => addout
);
a3: reg port map (
clk => clk,
rst => rst,
d => reg_in,
q => reg_out
);
lut: lut_table port map(
table_in => tablein,
table_out => tableout
);
add1 <= tableout;
add2 <= reg_out;
reg_in <= addout;
x0 <= data_in;
process(clk, enaa)
begin
if rising_edge(clk) and enaa = '1' then
x0 <= data_in;
x2 <= x1;
x3 <= x2;
x4 <= x3;
x5 <= x4;
x6 <= x5;
x7 <= x6;
x8 <= x7;
end if;
end process;
tap(0) <= (x8(0) & x7(0) & x6(0) & x5(0) & x4(0) & x3(0) & x2(0) & x1(0) & x0(0));
tap(1) <= (x8(1) & x7(1) & x6(1) & x5(1) & x4(1) & x3(1) & x2(1) & x1(1) & x0(1));
tap(2) <= (x8(2) & x7(2) & x6(2) & x5(2) & x4(2) & x3(2) & x2(2) & x1(2) & x0(2));
tap(3) <= (x8(3) & x7(3) & x6(3) & x5(3) & x4(3) & x3(3) & x2(3) & x1(3) & x0(3));
tap(4) <= (x8(4) & x7(4) & x6(4) & x5(4) & x4(4) & x3(4) & x2(4) & x1(4) & x0(4));
tap(5) <= (x8(5) & x7(5) & x6(5) & x5(5) & x4(5) & x3(5) & x2(5) & x1(5) & x0(5));
tap(6) <= (x8(6) & x7(6) & x6(6) & x5(6) & x4(6) & x3(6) & x2(6) & x1(6) & x0(6));
tap(7) <= (x8(7) & x7(7) & x6(7) & x5(7) & x4(7) & x3(7) & x1(7) & x1(7) & x0(7));
x0 <= data_in;
process(clk)
begin
if rst = '1' then
i <= "0000";
elsif rising_edge(clk) and i = "0001" then
enaa <= '1';
tablein <= tap(to_integer(i));
data_p <= tap(to_integer(i));
aaa <= i;
i <= i + "0001";
ena <= '1';
aaa <= i;
elsif rising_edge(clk) and i < "1000" then
i <= i + "0001";
enaa <= '0';
ena <= '0';
aaa <= i;
elsif rising_edge(clk) and i = "1000" then
enaa <= '0';
i <= "0001";
ena <= '0';
aaa <= i;
end if;
end process;
with enaa select
data_out <= reg_out when '1',
"00000000000000" when '0';
end arch;
I have big problems with top level file because I don't know how to put enter samples to lut table and create an fsm. Anyone helps ?
Regarding your Look Up Table, it will be easier to handle if you create it as Read Only Memory block.
Something like this:
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
entity lut_table is
port(
table_in : in std_logic_vector(8 downto 0);
table_out : out std_logic_vector(13 downto 0)
);
end lut_table;
Architecture ROM of lut_table is
-- Build a 2-D array type for the ROM
type rom_type is array (0 to 511) of std_logic_vector (13 downto 0);
constant rom_mem : rom_type := ("00000000000000",
"00000001101110",
"11111110111011",
...
"01010100000010"
);
begin
data_output <= rom_mem(conv_integer(address_in));
end ROM;
This way you can change its content fast.
Related
Flags for ALU in VHDL not updating when running simulation
So far everything works as intended except for the Cout (carryout) and V (overflow) when I simulate in the testbench. I get constant Us when performing addition and subtraction. I performed some of the calculations I'm testing by hand so I know which should have a carry value and overflow value. entity ALU is Port ( Cin : in STD_LOGIC_VECTOR ( 0 downto 0); ALUCntrl : in STD_LOGIC_VECTOR ( 3 downto 0); A, B : in STD_LOGIC_VECTOR (31 downto 0); ALUout : out STD_LOGIC_VECTOR (31 downto 0); Cout, Z, V : out STD_LOGIC ); end ALU; architecture Behavioral of ALU is SIGNAL result : STD_LOGIC_VECTOR (32 downto 0); SIGNAL bCout, bZ, bV : STD_LOGIC; begin WITH ALUCntrl SELECT result(31 downto 0) <= A and B when "0000", A or B when "0001", A xor B when "0011", std_logic_vector(unsigned(A) + unsigned(B) + unsigned(Cin)) WHEN "0010", std_logic_vector(unsigned(A) - unsigned(B)) WHEN "0110", A xnor B WHEN "1100", A xnor B WHEN "1111", "00000000000000000000000000000000" WHEN OTHERS; WITH result(31 downto 0) SELECT bZ <= '1' WHEN "00000000000000000000000000000000", '0' WHEN OTHERS; WITH ALUCntrl SELECT bCout <= result(32) WHEN "0010", result(32) WHEN "0110", '0' WHEN OTHERS; PROCESS(ALUCntrl) BEGIN CASE ALUCntrl IS WHEN "0010" =>-- Addition Overflow IF ((A(31) = '1') and (B(31) = '1') and (result(31) = '0')) THEN bV <= '1'; ELSIF ((A(31) = '0') and (B(31) = '0') and (result(31) = '1')) THEN bV <= '1'; ELSE bV <= '0'; END IF; WHEN "0110" => -- Subtraction overflow IF ((A(31) = '0') and (B(31) ='1') and (result(31) = '1')) THEN bV <= '1'; ELSIF ((A(31) = '1') and (B(31) = '0') and (result(31) = '0')) THEN bV <= '1'; ELSE bV <= '0'; END IF; WHEN OTHERS => bV <= '0'; END CASE; END PROCESS; ALUout <= result(31 downto 0); Cout <= bCout; Z <= bZ; V <= bV; end Behavioral; TEST-BENCH library IEEE; use IEEE.STD_LOGIC_1164.ALL; entity ALU_tb is -- Port ( ); end ALU_tb; architecture Behavioral of ALU_tb is -- INPUTS signal Cin : STD_LOGIC_VECTOR ( 0 downto 0); signal A, B : STD_LOGIC_VECTOR (31 downto 0); signal ALUCntrl : STD_LOGIC_VECTOR ( 3 downto 0); -- OUTPUTS signal ALUout : STD_LOGIC_VECTOR (31 downto 0); signal Cout, Z, V : STD_LOGIC; component ALU is port( Cin : in STD_LOGIC_VECTOR ( 0 downto 0); A, B : in STD_LOGIC_VECTOR (31 downto 0); ALUCntrl : in STD_LOGIC_VECTOR ( 3 downto 0); ALUout : out STD_LOGIC_VECTOR (31 downto 0); Cout, Z, V : out STD_LOGIC ); end component ALU; begin design_ALU: ALU port map( Cin => Cin, A => A, B => B, ALUCntrl => ALUCntrl, ALUout => ALUout, Cout => Cout, Z => Z, V => V ); tb : PROCESS BEGIN ALUCntrl <= "0000"; -- AND Cin <= "00"; A <= "11111111111111111111111111111111"; B <= "00000000000000000000000000000000"; wait for 250ns; ALUCntrl <= "0001"; -- OR A <= "10011000100110001001100010011000"; B <= "10001001100010011000100110001001"; wait for 250ns; ALUCntrl <= "0011"; -- XOR A <= "00000001000000010000000100000001"; B <= "00010000000100000001000000010000"; wait for 250ns; ALUCntrl <= "0010"; -- ADD A <= "00000000000000000000000000000001"; B <= "11111111111111111111111111111111"; wait for 250ns; ALUCntrl <= "0010"; -- ADD A <= "01100011100010010111010101001111"; B <= "10101101010101100010010011100110"; wait for 250ns; ALUCntrl <= "0010"; -- ADD Cin <= "01"; A <= "00000000000000000000000000000001"; B <= "11111111111111111111111111111111"; wait for 250ns; ALUCntrl <= "0010"; -- ADD A <= "01100011100010010111010101001111"; B <= "10101101010101100010010011100110"; wait for 250ns; ALUCntrl <= "0010"; -- ADD A <= "11111111111111111111111111111111"; B <= "11111111111111111111111111111111"; wait for 250ns; ALUCntrl <= "0110"; -- SUB A <= "00000000000000000000000000000000"; B <= "00000000000000000000000000000001"; wait for 250ns; ALUCntrl <= "0110"; -- SUB A <= "11111001011010000100011110000011"; B <= "11111001100110001101010101100010"; wait for 250ns; ALUCntrl <= "0110"; -- SUB A <= "10000000000000000000000000000000"; B <= "00000001000000000000000000000000"; wait for 250ns; ALUCntrl <= "1100"; -- NOR A <= "10011010101111001101111011011111"; B <= "10011010101111001101111011111101"; wait for 250ns; ALUCntrl <= "1111"; -- XNOR A <= "10001001101111001101111000110100"; B <= "11000101001110111101011010000111"; wait; END PROCESS tb; end Behavioral;
Error with VHDL port mapping an adder with unsigned variables
So i made a 4 bit adder, and I wanted it port mapped to an ALU I am building, yet for some reason the port map is coming up as an error. I have tried everything, changing variable types, changing the logic, and even changing variable names, but nothing works. The error pops up when I try to use the port map (the lines where it says bit0, bit1...), and the error complains about the work 'port' and ';'.
LIBRARY IEEE;
USE IEEE.std_logic_1164.ALL;
use ieee.numeric_std.all;
-- Define the input and output signals
ENTITY bit_FA IS
PORT (
A, B : in unsigned(7 downto 0);
CI : in std_logic;
SUM : out unsigned(7 downto 0);
CO : out std_logic);
END bit_FA;
-- Describe the full adder 's behavior
ARCHITECTURE bit_FA1 OF bit_FA IS
signal tmp: unsigned(8 downto 0);
begin
tmp <= A + B + ("0" & ci); --trick to promote ci to unsigned
SUM <= tmp(7 downto 0);
CO <= tmp(8);
END bit_FA1;
LIBRARY IEEE;
USE IEEE.std_logic_1164.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
use IEEE.numeric_std.ALL;
-- Define the input and output signals
ENTITY FinalLab IS
PORT (
CLK : in BIT;
code : in BIT_VECTOR;
A: in STD_LOGIC_VECTOR (3 downto 0);
B : inout STD_LOGIC_VECTOR (3 downto 0);
C, D : out STD_LOGIC_VECTOR (3 downto 0);
CO : out STD_LOGIC);
END FinalLab;
ARCHITECTURE behave_1 OF FinalLab IS
signal cin : std_logic_vector(3 downto 0);
component bit_FA is
port (
a, b, c : in std_logic;
sum, carry : out std_logic);
end component;
BEGIN
process(code)
begin
if code = "000" then
--error
bit0 : bit_FA port map( A(0), B(0), '0', C(0), cin(0));
bit1 : bit_FA port map ( A(1), B(1), carry(0), C(1), cin(1) );
bit2 : bit_FA port map ( A(2), B(2), carry(1), C(2), cin(2) );
bit3 : bit_FA port map ( A(3), B(3), carry(2), C(3), cin(3) );
CO <= cin(3);
elsif code = "001" then
C(0) <= A(3);
C(1) <= A(2);
C(2) <= A(1);
C(3) <= A(0);
elsif code = "010" then
--multiplication
B <= std_logic_vector( unsigned(B) - 1 );
elsif code = "011" then
C <= std_logic_vector( unsigned(A) + 1 );
elsif code = "100" then
C(0) <= not(A(0) XOR B(0));
C(1) <= not(A(1) XOR B(1));
C(2) <= not(A(2) XOR B(2));
C(3) <= not(A(3) XOR B(3));
elsif code = "101" then
C(0) <= not A(0);
C(1) <= not A(1);
C(2) <= not A(2);
C(3) <= not A(3);
elsif code = "110" then
C(0) <= A(3);
C(1) <= A(0);
C(2) <= A(1);
C(3) <= A(2);
elsif code = "111" then
C(0) <= A(1);
C(1) <= A(2);
C(2) <= A(3);
C(3) <= A(0);
end if;
end process;
END behave_1;
VHDL stands for VHSIC Hardware Description Language. As it is hardware, you cannot use if-statements and such to make components magically appear and disappear. All components need to be connected all the time. What you can do is implement switched/multiplexers to select the output of components. However, you need intermediate signals. I.e., the full adders need to be connected in the architecture scope and the output selected in the if statement ARCHITECTURE behave_1 OF FinalLab IS signal FA_out : std_logic_vector(3 downto 0); [...] begin bit0 : bit_FA port map( A(0), B(0), '0', FA_out(0), cin(0)); bit1 : bit_FA port map ( A(1), B(1), cin(0), FA_out(1), cin(1) ); bit2 : bit_FA port map ( A(2), B(2), cin(1), FA_out(2), cin(2) ); bit3 : bit_FA port map ( A(3), B(3), cin(2), FA_out(3), cin(3) ); [...] if code = "000" then C <= FA_out; CO <= cin(3); [...] Note: the CLK input port is there for a reason... use it.
VHDL synthesis tool won't infer FSM
I'm trying to create a FSM in VHDL. However, the synthesis tool that I'm using (Vivado) won't infer it, and instead it thinks I've created a lot of registers and mux. The goal of the hardware I'm designing is to implement a locker onto a FPGA. I've changed a lot of things in order not to create any latch, so if you see something wrong please tell me. Also, I'm Spanish so some names are in Spanish; if you don't understand something please tell me. I don't know if you need something else like the synthesis report. (Please don't tell me to create just one process, I have to design it using one sequential and one combinational process). Here's the code: library ieee; use ieee.std_logic_1164.all; use ieee.numeric_std.all; entity cerrojo is port ( boton : in std_logic; rst : in std_logic; clk : in std_logic; clave : in std_logic_vector(7 downto 0); leds : out std_logic_vector(15 downto 0); intentos: out std_logic_vector(6 downto 0)); end cerrojo; architecture archCerrojo of cerrojo is signal intentos_binario : unsigned(3 downto 0); signal sin_rebote : std_logic; signal guardado : unsigned(7 downto 0); type estado is(inicial, tres, dos, uno, final); signal estado_actual, estado_siguiente : estado; component conv_7seg is port (x : in std_logic_vector (3 downto 0); display : out std_logic_vector (6 downto 0)); end component conv_7seg; component debouncer is port ( rst : in std_logic; clk : in std_logic; x : in std_logic; xdeb : out std_logic; xdebfallingedge : out std_logic; xdebrisingedge : out std_logic); end component debouncer; begin sieteSeg : conv_7seg port map ( x => std_logic_vector(intentos_binario(3 downto 0)), display => intentos); rebotes : debouncer port map (rst => rst, clk => clk, x => boton, xdeb => sin_rebote); p_reg : process(clk, rst) begin if rst = '1' then guardado <= "00000000"; estado_actual <= inicial; elsif rising_edge(clk) and estado_actual = inicial then guardado <= unsigned(clave); estado_actual <= estado_siguiente; elsif rising_edge(clk) then guardado <= guardado; estado_actual <= estado_siguiente; end if; end process p_reg; p_comb : process(estado_actual, sin_rebote, clave, guardado) begin case estado_actual is when inicial => intentos_binario <= "1000"; leds <= "1111111111111111"; --guardado <= unsigned(clave); if (sin_rebote = '1') then estado_siguiente <= tres; else estado_siguiente <= inicial; end if; when tres => intentos_binario <= "0011"; leds <= "0000000000000000"; -- guardado <= guardado; if (sin_rebote = '1' and guardado = unsigned(clave)) then estado_siguiente <= inicial; elsif (sin_rebote = '1' and guardado /= unsigned(clave)) then estado_siguiente <= dos; else estado_siguiente <= tres; end if; when dos => intentos_binario <= "0010"; leds <= "0000000000000000"; --guardado <= guardado; if (sin_rebote = '1' and guardado = unsigned(clave)) then estado_siguiente <= inicial; elsif (sin_rebote = '1' and guardado /= unsigned(clave)) then estado_siguiente <= uno; else estado_siguiente <= dos; end if; when uno => intentos_binario <= "0001"; leds <= "0000000000000000"; --guardado <= guardado; if (sin_rebote = '1' and guardado = unsigned(clave)) then estado_siguiente <= inicial; elsif (sin_rebote = '1' and guardado /= unsigned(clave)) then estado_siguiente <= final; else estado_siguiente <= uno; end if; when final => intentos_binario <= "0000"; leds <= "0000000000000000"; --guardado <= guardado; estado_siguiente <= final; end case; end process p_comb; end architecture archCerrojo; Thank you in advance!
Simple VHDL ALU will not show inputs or overflow in the waveform
I'm supposed to write up a 16-bit ALU. My professor wants us to try and code the adder and sub of the ALU with a signal tmp : std_logic_vector(16 downto 0); and then in the case for the select input s we put: tmp <= conv_std_logic_vector(conv_integer(a) + conv_integer(b), 17); After experimenting with it for a while, my waveform only showed the inputs' values as UUUUUUUUUUUUUUUU. Even after I had commented out the conv_std_logic_vector(...) stuff. Is there a simple explanation as to why my inputs aren't showing up in the waveform? Here is my code: -- 16-Bit ALU -- By: Logan Jordon library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_unsigned.all; use IEEE.NUMERIC_STD.ALL; --use ieee.std_logic_arith.all; entity alu16 is port ( a : in std_logic_vector(15 downto 0); b : in std_logic_vector(15 downto 0); s : in std_logic_vector(1 downto 0); r : out std_logic_vector(15 downto 0); cout : out std_logic; lt, eq, gt : out std_logic; overflow : out std_logic ); end entity alu16; architecture beh of alu16 is signal tmp : std_logic_vector(16 downto 0); signal add_overflow : std_logic; signal sub_overflow : std_logic; begin -- PROCESS process(a, b, add_overflow, sub_overflow) begin case s is --ADD when "00" => --tmp <= conv_std_logic_vector(conv_integer(a) + conv_integer(b), 17); tmp <= a + b; overflow <= add_overflow; --SUB when "01" => --tmp <= conv_std_logic_vector(conv_integer(a) - conv_integer(b), 17); tmp <= a - b; overflow <= sub_overflow; --AND when "10" => tmp <= '0' & a AND b; overflow <= '0'; --OR when "11" => tmp <= '0' & a OR b; overflow <= '0'; when others => tmp <= "00000000000000000"; end case; --One-Bitters if a > b then gt <= '1'; lt <= '0'; eq <= '0'; elsif a < b then lt <= '1'; gt <= '0'; eq <= '0'; elsif a = b then eq <= '1'; lt <= '0'; gt <= '0'; end if; end process; --OUTPUTS cout <= tmp(16); r <= tmp(15 downto 0); add_overflow <= '1' when (a(15) = b(15)) and (a(15) /= tmp(15)) else '0'; sub_overflow <= '1' when (a(15) = NOT b(15)) and (a(15) /= tmp(15)) else '0'; end beh; EDIT: In the case that it might be my test bench, here's the code for my testbench: library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_unsigned.all; use IEEE.NUMERIC_STD.ALL; entity alu16_tb is end alu16_tb; architecture behavior of alu16_tb is component ALU16 port( a : in std_logic_vector(15 downto 0); b : in std_logic_vector(15 downto 0); s : in std_logic_vector(1 downto 0); r : out std_logic_vector(15 downto 0); cout : out std_logic; lt, eq, gt : out std_logic; overflow : out std_logic ); end component; -- Signals to interface with the UUT -- Set each of the input vectors to unique values to avoid -- needing a process to drive them below signal a : std_logic_vector(15 downto 0) := "0000000000000000"; signal b : std_logic_vector(15 downto 0) := "0000000000000000"; signal s : std_logic_vector(1 downto 0) := "00"; signal r : std_logic_vector(15 downto 0):= "0000000000000000"; signal cout : std_logic := '0'; signal lt : std_logic := '0'; signal gt : std_logic := '0'; signal eq : std_logic := '0'; signal overflow : std_logic := '0'; constant tick : time := 10 ns; begin -- Instantiate the Unit Under Test (UUT) uut : ALU16 port map ( a => a, b => b, s => s, r => r, cout => cout, lt => lt, gt => gt, eq => eq, overflow => overflow ); -- Drive selector bits drive_s : process begin a <= "0000000000000001"; b <= "0000000000000010"; wait for (tick*2); s <= "00"; wait for (tick*2); s <= "01"; wait for (tick*2); s <= "10"; wait for (tick*2); s <= "11"; end process drive_s; end;
VHDL 10500 : error syntax near text
I have this vhdl code : library ieee; use ieee.std_logic_1164.all; use ieee.numeric_std.all; entity avalon_fir_4 is port ( clk, reset: in std_logic; -- avalon interface gcd_address: in std_logic_vector(2 downto 0); -- 3-bit address gcd_chipselect: in std_logic; gcd_write: in std_logic; gcd_writedata: in std_logic_vector(31 downto 0); gcd_readdata: out std_logic_vector(31 downto 0)); end avalon_fir_4; architecture arch of avalon_fir_4 is signal i_coeff_0 : std_logic_vector( 31 downto 0); signal i_coeff_1 : std_logic_vector( 31 downto 0); signal i_coeff_2 : std_logic_vector( 31 downto 0); signal i_coeff_3 : std_logic_vector( 31 downto 0); -- data input signal i_data : std_logic_vector( 31 downto 0); -- filtered data signal o_data : std_logic_vector( 31 downto 0); signal wr_en, wr_a, wr_b, wr_c, wr_d, wr_e: std_logic; type state_type is (idle, count); signal state_reg, state_next: state_type; signal c_reg, c_next: unsigned(15 downto 0); begin fir_unit: fir_filter_4 port map(clk, reset, i_coeff_0, i_coeff_1, i_coeff_2, i_coeff_3, i_data, o_data); process (clk, reset) begin --if reset=’1’ then --o_data <= (others=>(others=>'0')); --data <= (others=>(others=>'0')); --i_coeff_0 <= (others=>(others=>'0')); --i_coeff_1 <= (others=>(others=>'0')); --i_coeff_2 <= (others=>(others=>'0')); --i_coeff_3 <= (others=>(others=>'0')); --elsif (clk'event and clk=’1’) then if wr_a=’1’ then i_data <= gcd_writedata; elsif wr_b=’1’ then i_coeff_0 <= gcd_writedata; elsif wr_c='1' then i_coeff_1 <= gcd_writedata; elsif wr_d='1' then i_coeff_2 <= gcd_writedata; elsif wr_e='1' then i_coeff_3 <= gcd_writedata; end if; --end if; end process; wr_en <=’1’ when gcd_write=’1’ and gcd_chipselect=’1’ else ’0’; wr_a <= ’1’ when gcd_address="000" and wr_en=’1’ else ’0’; wr_b <= ’1’ when gcd_address="001" and wr_en=’1’ else ’0’; wr_c <= ’1’ when gcd_address="010" and wr_en=’1’ else ’0’; wr_d <= ’1’ when gcd_address="011" and wr_en=’1’ else ’0’; wr_e <= ’1’ when gcd_address="100" and wr_en=’1’ else ’0’; gcd_start <= ’1’ when gcd_address="010" and wr_en=’1’ else ’0’; gcd_readdata <= r_out when gcd_address="100" else gcd_ready & "000" & x"000" & std_logic_vector(c_reg); end arch; compilation crash : I have tried many ways of writing the vhdl at multiple places without success. What is this error?