I'm creating a new project which i called alpha,then i create a new file test.vhd.
library ieee;
use ieee.std_logic_1164.all;
entity d_latch is
port(
data_in:in std_logic;
data_out:out std_logic;
enable:in std_logic);
end d_latch;
architecture beh of d_latch is
begin
process(data_in,enable)
begin
if(enable <= '1') then
data_out <= data_in;
end if;
end process;
end beh;
I add test.vhd to the project alpha then i compile the file.After that i simulate->start simulate then i check [+] work library then the module presented in it,but an error's message appears
Error loading design
First edit the if statement to get the correct results :
if(enable <= '1') must be if(enable = '1')
I simulated your code and no errors found. Simulation results was correct.
Just open modelsim software, click file and change directory (for example to the address of test.vhd file)
Then compile test.vhd and simulate it. Sometimes you should close modelsim and do the same stages again, because the library directory may be changed wrongly by yourself.
I've had similar problems with Modelsim, even when just making minor changes to the VHDL code and recompiling. One thing that seems to work is to change the port modes from buffer to out or inout, depending on the design.
Related
Good day! I have a following issue:
I am using Xilinx ISE 14.5 to design for a Spartan 6 FPGA. I noticed that is one of my designs I wasn't able to change the physical pin mapping for a signal. When I changed the line in the .ucf file to another physical pin, re-synthesized and re-implemented the design and uploaded new .bit file the actual signal was still being routed to the old pin.
After that I completely cleared the .ucf file and again rerun the synthesis, implementation etc. and the software didn't even give me a warning about the missing pin declarations.
Here's my code:
entity top is
port(
i_clk : IN STD_LOGIC;
o_test3 : INOUT STD_LOGIC := '1'
);
end top;
architecture Behavioral of top is
begin
p_test: process (i_clk) begin
if rising_edge(i_clk) then
o_test3 <= not o_test3;
end if;
end process;
end Behavioral;
enter code here
The .ucf file is completely empty. I expect the software to raise a warning about the missing declaration of i_clk and o_test3. Is my understanding wrong?
If it should raise a warning, is this a bug that can be helped? I am thinking of installing 14.7 version in hopes that it would fix the issue but I thought I'd ask about any possible solutions first. Thanks in advance.
If no LOC constraint for a pin is provided in a UCF file, ISE will choose a location for the pin. I don't recall if it provides a warning or not.
14.7 offers only minor differences to 14.5 so upgrading is not likely to change anything in your case.
Without the UCF file, we can't really help you with why the LOC constraint isn't being honored.
I am getting this messege from compiler for all the "busreg" bits:
topld: busshift.vhd: (E463) 'busreg(7)' -- Can't handle registered multi driver.
topld: busshift.vhd: (E446) Can't handle multiple drivers for 'busreg(7)' in selected device.
I was asked to do shift rigister that I can put in put from both side as I choose depends on DIR.
My code:
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
use ieee.std_logic_arith.all;
ENTITY shiftbus IS
PORT
(
busreg : inout std_logic_vector(7 downto 0);
dir,clk : IN std_logic;
pinL,pinR : inout std_logic
);
END shiftbus;
ARCHITECTURE behavioral OF shiftbus IS
BEGIN
busreg<="00000000";
process(clk,dir)
begin
if (rising_edge(clk)) then
if(dir='1') then --1 we input from right
busreg<=busreg(6 downto 0)&pinR;
else-- else is 0 and we input from left
busreg<=pinL & busreg(7 downto 1);
end if;
end if;
end process;
END behavioral;
You have the following line:
busreg <= "00000000";
If you're going to drive this signal low all the time, what's the point of the other logic?
You are driving the signal busreg from two processes: the explicit process and the implicit process busreg <= "00000000";. In other words, you have a short circuit.
A process is a little bit of software that models a little bit of hardware.
So, when you drive a signal from more than one process, you are modelling a signal that is driven from more than one lump of hardware. Normally, if you want to drive a signal from two or more lumps of hardware, you need to be using tristate logic. I think the error message is telling you that the FPGA device you have chosen is not able to implement tristate logic and so it is an error for you to drive a signal from more that one place.
So, why have you written the line busreg <= "00000000";? If you were hoping to reset your shift register, you haven't; you've created a short circuit.
BTW: your process is a sequential process. The sensitivity list of a sequential process should either contain just the clock or, if there is an asynchronous reset, just the clock and the asynchronous reset. dir should not be in your sensitivity list.
I recently started working with FPGAs and have been trying to get a basic VHDL program up and running. My code is intended to take the inputs from 10 switches and map them to 10 LED outputs on my dev board, but when I attempt to run analysis/synthesis I get the error in the title. Analyzing the file individually by running "Analyze Current File" yields no errors. A similar post was made here, but the solution there does not help me. I have only one file in my project and I am certain that it has been specified as the top-level entity.
library IEEE; use IEEE.STD_LOGIC_1164.all;
entity sw_to_led is port(
SW: in bit_vector(9 downto 0);
LED: out bit_vector(9 downto 0));
end sw_to_led;
architecture behavior of sw_to_led is
begin
LED <= SW after 5ns;
end behavior;
I thought that the top-level file had to have the same name as the specified "top-level design entity", instead of the entity itself. I learned to read and changed the name of the actual entity to match what was specified and it fixed the issue.
1) Is the name of the vhdl file the same as the entity name sw_to_led.vhd ?
2) Are there already partitions in your design? If yes, you can try making a new Quartus-Project with the help of the "New Project Wizard" and add only the file sw_to_led.vhd.
By the way, after 5ns is not synthesizable. It should only be used in the simulation. But for Quartus it's not an error.
I am spending some time learning about writing test benches to try out on some of the models I have produced. Does anyone know a way to monitor signals that are internal to the architecture of the unit under test. I have tried using
LIBRARY MODELSIM_LIB;
USE MODELSIM_LIB.UTIL.ALL;
spy_process : process begin
init_signal_spy("Q4/C1/A1/chip_sel","/chip_sel",1);
wait;
end process spy_process;
But I get a compiler error of the :
Error (10481): VHDL Use Clause error at Q4.vhd(15): design library "MODELSIM_lib" does not contain primary unit "util"
I've checked the Quartus II library folder and util is there in the correct place.
Any suggestions?
Thanks D
When you start a simulation, Quartus analyzes all files specified in the project settings (accessible via menu Assignment -> Settings -> Files). But, it elaborates only the entities which are required for the DUT starting from the top-level entity (see menu Assignment -> Settings -> General) to find out which design files (excluding testbenches) are required for simulation.
For more details, see my other answer.
The library MODELSIM_LIB is found by ModelSim only, not by Quartus. Thus, Quartus-II fails to analyze your testbench file with the error posted in the question. But this is actually not required because it (should) only contain testbench code. Thus:
remove this testbench file from your Quartus project via menu Project -> "Add/Remove Files in Project...", and
add this file only in the simulation settings accessible via menu Assignment -> Settings -> Simulation -> Compile test bench -> Test Benches -> New/Edit.
Presumably you are using Modelsim to simulate, in which case you should not need anything more than to use the signal spy in VHDL, here is an example (excuse any syntax errors)...
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity my_testbench is
end my_testbench;
architecture behavioral of my_testbench is
signal spy_blob : std_logic := '0';
begin
my_entity : entity work.my_entity(rtl)
port map(
...
);
spy_blob <= << signal .my_testbench.my_entity.w_blob : std_logic >>;
my_monitor : process(w_clk)
begin
if(rising_edge(w_clk)) then
if(spy_blob = '1') then
-- do something
end if;
end if;
end process;
end behavioral;
Note: this works with V13 of Quartus/Modelsim package.
I am making some kind of cache and i am using some tables (big ones) inside entity which are composed of std_logic_vectors and i am doing it in Quartus 2 web edition.
Everything works fine in simulation, but when i try to synthesize it its being done ONLY with latches, AND and OR components.
Is there any way to specify Quartus to use memory modules for those tables instead of these combination elements? Or maybe something can be done from VHDL code itself.
library ieee;
use ieee.std_logic_1164.all;
package UTIL_PACK is
type matrix16x8 is array (0 to 15) of std_logic_vector(0 to 7);
type matrix2p4x8 is array (0 to 2**4) of matrix16x8;
end package;
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.util_pack.all;
entity RAM16B is
port(
signal RD: in std_logic;
signal WR: in std_logic;
signal CLK: in std_logic;
signal A: in std_logic_vector(7 downto 0);
signal D: inout matrix16x8;
signal FC: out std_logic
);
end entity ;
architecture RAM16B_IMPL of RAM16B is
signal memory: matrix2p4x8 := ((others => (others => (others => 'Z'))));
begin
run:process(clk)is
variable slot:integer range 0 to 15 :=0;
begin
if(clk='1') then
slot := TO_INTEGER(unsigned(A)) rem 16;
if(rd = '1')then
FC<='0';
for i in 0 to 3 loop
D(i) <= memory(i)(slot);
end loop;
FC<='1';
elsif(wr = '1')then
FC<='0';
for i in 0 to 3 loop
memory(i)(slot) <= D(i);
end loop;
FC<='1';
else
FC <= 'Z';
D <= ( others => ( others => 'Z' ));
end if;
else
FC <= 'Z';
D <= ( others => ( others => 'Z' ));
end if;
end process;
end architecture RAM16B_IMPL;
RAM consists of 16 blocks of memory, each block is 16 bytes. I am trying to read more data parallely so I am reading/writing 16 bytes of data per cycle. Slot defines block in which reading/writing is being done.
If you really want to make sure you use the hard memory blocks, you should either use the mega-function wizard to craft a custom ram component, or directly instantiate an altsyncram component from the library and use the generics to configure it how you want (this can be tricky if you're not extremely familiar with the options). This causes porting issues, but any time you infer ram you generally have porting issues anyway. Using a custom library component just makes it very obvious and easy to identify where you might have problems if you ever do need to migrate to something else.
As for your specific implementation, there's no way you're going to get latches automatically migrated into the hard ram blocks which are edge driven devices. Use rising_edge(clk) instead of clk='1' in your process to fix this.
Also, there is no support for tri-state operation internal to the chip, you need independent data in and data out ports. You are getting lots of discrete logic because and & or gates are being used to emulate a tri-state bus (and because of the latch issue, above).
Yes, you can do it from your VHDL code. To make sure that Quartus understands that you are modeling a memory, you should code it as described in Altera's Recommended HDL Coding Styles guide. Take a look at the section called Inferring Memory Functions from HDL Code (http://www.altera.com/literature/hb/qts/qts_qii51007.pdf), then modify your code accordingly.
It is probably a good idea to start with the exact memory model suggested by Altera, and making sure that Quartus synthesizes the design using the FPGA's dedicated memory bits. Next, you can gradually change your model to implement the desired behavior, always synthesizing and looking at the compilation reports to make sure your changes didn't deviate from what Quartus infers as a memory block.