I recently started working with FPGAs and have been trying to get a basic VHDL program up and running. My code is intended to take the inputs from 10 switches and map them to 10 LED outputs on my dev board, but when I attempt to run analysis/synthesis I get the error in the title. Analyzing the file individually by running "Analyze Current File" yields no errors. A similar post was made here, but the solution there does not help me. I have only one file in my project and I am certain that it has been specified as the top-level entity.
library IEEE; use IEEE.STD_LOGIC_1164.all;
entity sw_to_led is port(
SW: in bit_vector(9 downto 0);
LED: out bit_vector(9 downto 0));
end sw_to_led;
architecture behavior of sw_to_led is
begin
LED <= SW after 5ns;
end behavior;
I thought that the top-level file had to have the same name as the specified "top-level design entity", instead of the entity itself. I learned to read and changed the name of the actual entity to match what was specified and it fixed the issue.
1) Is the name of the vhdl file the same as the entity name sw_to_led.vhd ?
2) Are there already partitions in your design? If yes, you can try making a new Quartus-Project with the help of the "New Project Wizard" and add only the file sw_to_led.vhd.
By the way, after 5ns is not synthesizable. It should only be used in the simulation. But for Quartus it's not an error.
Related
Good day! I have a following issue:
I am using Xilinx ISE 14.5 to design for a Spartan 6 FPGA. I noticed that is one of my designs I wasn't able to change the physical pin mapping for a signal. When I changed the line in the .ucf file to another physical pin, re-synthesized and re-implemented the design and uploaded new .bit file the actual signal was still being routed to the old pin.
After that I completely cleared the .ucf file and again rerun the synthesis, implementation etc. and the software didn't even give me a warning about the missing pin declarations.
Here's my code:
entity top is
port(
i_clk : IN STD_LOGIC;
o_test3 : INOUT STD_LOGIC := '1'
);
end top;
architecture Behavioral of top is
begin
p_test: process (i_clk) begin
if rising_edge(i_clk) then
o_test3 <= not o_test3;
end if;
end process;
end Behavioral;
enter code here
The .ucf file is completely empty. I expect the software to raise a warning about the missing declaration of i_clk and o_test3. Is my understanding wrong?
If it should raise a warning, is this a bug that can be helped? I am thinking of installing 14.7 version in hopes that it would fix the issue but I thought I'd ask about any possible solutions first. Thanks in advance.
If no LOC constraint for a pin is provided in a UCF file, ISE will choose a location for the pin. I don't recall if it provides a warning or not.
14.7 offers only minor differences to 14.5 so upgrading is not likely to change anything in your case.
Without the UCF file, we can't really help you with why the LOC constraint isn't being honored.
I am spending some time learning about writing test benches to try out on some of the models I have produced. Does anyone know a way to monitor signals that are internal to the architecture of the unit under test. I have tried using
LIBRARY MODELSIM_LIB;
USE MODELSIM_LIB.UTIL.ALL;
spy_process : process begin
init_signal_spy("Q4/C1/A1/chip_sel","/chip_sel",1);
wait;
end process spy_process;
But I get a compiler error of the :
Error (10481): VHDL Use Clause error at Q4.vhd(15): design library "MODELSIM_lib" does not contain primary unit "util"
I've checked the Quartus II library folder and util is there in the correct place.
Any suggestions?
Thanks D
When you start a simulation, Quartus analyzes all files specified in the project settings (accessible via menu Assignment -> Settings -> Files). But, it elaborates only the entities which are required for the DUT starting from the top-level entity (see menu Assignment -> Settings -> General) to find out which design files (excluding testbenches) are required for simulation.
For more details, see my other answer.
The library MODELSIM_LIB is found by ModelSim only, not by Quartus. Thus, Quartus-II fails to analyze your testbench file with the error posted in the question. But this is actually not required because it (should) only contain testbench code. Thus:
remove this testbench file from your Quartus project via menu Project -> "Add/Remove Files in Project...", and
add this file only in the simulation settings accessible via menu Assignment -> Settings -> Simulation -> Compile test bench -> Test Benches -> New/Edit.
Presumably you are using Modelsim to simulate, in which case you should not need anything more than to use the signal spy in VHDL, here is an example (excuse any syntax errors)...
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity my_testbench is
end my_testbench;
architecture behavioral of my_testbench is
signal spy_blob : std_logic := '0';
begin
my_entity : entity work.my_entity(rtl)
port map(
...
);
spy_blob <= << signal .my_testbench.my_entity.w_blob : std_logic >>;
my_monitor : process(w_clk)
begin
if(rising_edge(w_clk)) then
if(spy_blob = '1') then
-- do something
end if;
end if;
end process;
end behavioral;
Note: this works with V13 of Quartus/Modelsim package.
I'm creating a new project which i called alpha,then i create a new file test.vhd.
library ieee;
use ieee.std_logic_1164.all;
entity d_latch is
port(
data_in:in std_logic;
data_out:out std_logic;
enable:in std_logic);
end d_latch;
architecture beh of d_latch is
begin
process(data_in,enable)
begin
if(enable <= '1') then
data_out <= data_in;
end if;
end process;
end beh;
I add test.vhd to the project alpha then i compile the file.After that i simulate->start simulate then i check [+] work library then the module presented in it,but an error's message appears
Error loading design
First edit the if statement to get the correct results :
if(enable <= '1') must be if(enable = '1')
I simulated your code and no errors found. Simulation results was correct.
Just open modelsim software, click file and change directory (for example to the address of test.vhd file)
Then compile test.vhd and simulate it. Sometimes you should close modelsim and do the same stages again, because the library directory may be changed wrongly by yourself.
I've had similar problems with Modelsim, even when just making minor changes to the VHDL code and recompiling. One thing that seems to work is to change the port modes from buffer to out or inout, depending on the design.
I have a memory module for an Altera FPGA target that I've written to be inferred into one of Altera's ALTSYNCRAM blocks. The memory is 1024x16 and I have a memory initialization file specified with an attribute.
When synthesizing, the synthesis report indicates that it generated the type of RAM block that I wanted, and it notes that the initialization file is the one I specified.
When trying to simulate with Altera's edition of ModelSim, the data signal starts out completely uninitialized, and I can't figure out why.
I looked on forums and such and some people mentioned that ModelSim might not support the ".mif" format that I was using, but would support ".hex" so I changed my initialization file to ".hex". I also read that relative file paths can be an issue, but I checked my simulation directory and it looks like QuartusII copied the initialization file into that directory when I tried to simulate.
Any ideas on why the memory isn't being initialized and how to make it do so?
A heavily trimmed model that contains the inferred memory:
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library work;
--use work.types.all;
entity CPU is
--...
end entity CPU;
architecture rtl of CPU is
--these types are actually included in a package
subtype reg is std_logic_vector(15 downto 0);
type mem is array (0 to 1023) of reg;
--...
--memory read port
signal MR : reg;
signal MRA : std_logic_vector(9 downto 0); --flops
--memory write port
signal MW : reg; --flops
signal MWA : std_logic_vector(9 downto 0); --flops
signal MWE : std_logic; --flop
signal data : mem;
attribute ram_init_file : string;
attribute ram_init_file of data : signal is "RAM_init.hex";
attribute ramstyle : string;
attribute ramstyle of data : signal is "no_rw_check";
begin
--...
--memory spec
MR <= data(to_integer(unsigned(MRA(9 downto 0))));
memory_process : process(clk)
begin
if (clk'event and clk = '1') then
if(MWE = '1') then
data(to_integer(unsigned(MWA(9 downto 0)))) <= MW;
end if;
end if;
end process;
end architecture rtl; --CPU
Modelsim does not show any warnings or errors while compiling CPU.vhd, nor does it have any indication of loading the initialization file.
This is my first design using Altera software or memory initialization files, and it wouldn't surprise me if the problem was something really basic, or I'm approaching this from a fundamentally incorrect angle.
I'd normally define the memory with a constant in a package, but this is for a class, and it requires that I have a memory initialization file (it requires .mif format too, but that's only a 3 character change between simulation and synthesis file).
It looks like Modelsim may have a "mem load" command you can use at the start of your simulation in order to initialize the memory. Take a look at the end of this thread:
Initialization altsyncram
Being able to initialize RAM on an FPGA depends on both the synthesizer and the specific FPGA you are using. Some FPGA families support this, others don't. I know this is not the answer you want to hear, but you'll need to check the documentation from Altera.
Modelsim does not pay attention to synthesis attributes. That is a vendor specific convention. You can refer to them in simulation as with any other user-defined attribute but it doesn't know that some attributes invoke special behavior in various third-party synthesizers.
If you want to initialize the RAM for simulation you will need to do one of the following:
Write a function that reads the contents of the memory file and call it during initialization of the data signal.
Convert the memory contents to a VHDL constant defined in a separate package and assign the constant to the data signal as the initializer. This can be automated with a script.
Use the Verilog system task $readmemh (requires Modelsim with mixed language license)
For option 1, the function should be of the form:
impure function read_mem(fname : string) return mem is
variable data : mem;
begin
-- ** Perform read with textio **
...
return data;
end function;
signal data : mem := read_mem(data'ram_init_file);
The Quartus documentation on RAM initialization is sparse and only demonstrates initialized data assigned from within a VHDL process rather than reading from a file. The Xilinx documentation on RAM/ROM inferencing (p258) provides examples for doing this with general purpose VHDL. The same technique can be used for simulating a design targeted to Altera. XST supports this use of file I/O for synthesis but Quartus may choke on it. If that is the case you will have to use a configuration to swap between a synthesis oriented RAM model and one specifically for simulation that initializes with the function.
The Xilinx example only shows how to read files with ASCII binary. I have a general purpose ROM component that reads hex as well as binary which you can adapt into a RAM for what you need.
I got WebPack up and running on my machine again and after synthesizing a simple design and uploading it to my FPGA, I encountered quite a problem with my understanding.
When there is a line like this in the user constraint file:
NET "W1A<0>" LOC = "P18" ;
How exactly does the synthesis software determine how this pin gets assigned to by the VHDL code?
For instance, take this example code I've been provided with:
entity Webpack_Quickstart is
Port (
W1A : out STD_LOGIC_VECTOR(15 downto 0);
rx : in STD_LOGIC;
tx : inout STD_LOGIC;
clk : in STD_LOGIC
);
end Webpack_Quickstart;
architecture Behavioral of Webpack_Quickstart is
signal counter : STD_LOGIC_VECTOR(47 downto 0) := (others => '0');
begin
W1A(0) <= '1';
end;
How exactly does this code make the WIA0 pin on my FPGA turn on? What is the link? Is it just the name of the port in the entity declaration is there more magic involved?
Your .ucf constraints are applied in the implementation phase. At this point your design has been synthesized, and the available top-level nets are thus "known". So yes, it is only a matter of matching equally named nets to equally named constraints.
The syntax is slightly different though (using <> instead of () for indexing vectors for instance), but otherwise it's just a simple string match.
The easiest way to initially configure your pin constraints, especially for large designs, is to just use one of the graphical tools (PlanAhead, if it's included in the WebPack) to assign the pins, and generate an initial .ucf file.
I find that making small changes later on is easiest to do by hand using the standard ISE text editor directly though.