VHDL 2008 and CASE statement - vhdl

Question

I've a question about a case statement and VHDL 2008. I've an entity defined in this way :
entity multiplier_v2 is
generic( WIDTH_WORD : integer := 32;
WIDTH_RSA : integer := 2048;
LENGTH_ADDRESS : integer := 6 );
port (
reset : in std_logic;
clk : in std_logic;
start : in std_logic;
input_1 : in std_logic_vector(WIDTH_WORD - 1 downto 0);
input_2 : in std_logic_vector(WIDTH_WORD - 1 downto 0);
module : in std_logic_vector(WIDTH_WORD - 1 downto 0);
output : out std_logic_vector(WIDTH_WORD - 1 downto 0);
ack_data : out std_logic;
data_valid : out std_logic;
new_module : in std_logic;
Inside the module I've a signal declared in this way :
signal counter_ack : std_logic_vector(LENGTH_ADDRESS - 1 downto 0);
I use this signal in a case statement :
case counter_ack is
when (others => '1') =>
ack_data <= '0';
when others =>
counter_ack <= counter_ack + 1;
end case;
Now, I'm pretty sure that VHDL-2008 option is enabled in my synthesis tool but I have the following error regarding that part of my code:
2049990 ERROR - E:/My_Designs/Custom Module/Montgomery_Multiplier/Diamond/src/multiplier_v2.vhd(456,6-461,15) (VHDL-1544) array type case expression must be of a locally static subtype
I've read that this error should be fixed in VHDL-2008. Any ideas ?

Answer 1

I compiled the code displayed below in Quartus II with VHDL 2008 compiler option. I got no error. Does your case statement is in a process?
LIBRARY ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.std_logic_signed.all;
ENTITY casestate IS
generic( WIDTH_WORD : integer := 32;
WIDTH_RSA : integer := 2048;
LENGTH_ADDRESS : integer := 6 );
port (
reset : in std_logic;
clk : in std_logic;
ack_data : out std_logic
);
END casestate;
ARCHITECTURE fpga OF casestate IS
signal counter_ack : std_logic_vector(LENGTH_ADDRESS - 1 downto 0);
BEGIN
process(clk,reset)
begin
if(reset = '0')then
ack_data <= '0';
elsif(rising_edge(clk))then
case counter_ack is
when (others => '1') =>
ack_data <= '0';
when others =>
counter_ack <= counter_ack + 1;
ack_data <= '1';
end case;
end if;
end process;
end fpga;

Answer 2

You need to specify the range, (others => '1') is an unconstrained vector
So you could do something like
when (counter_ack'range => '1') =>
which is a vector of defined length that should work in more software that doesn't make inferences.
this also works for if statements
if VEC = (VEC'range => '0') then
CODE
end if;