How works intruction mod in the vhdl program? - vhdl

Question

I just have one doubt with the following program:
process(clk)
variable cuenta : integer range 0 to 255 := 0;
begin
if clk = '1' and clk'event then
cuenta := (cuenta +1) mod 256;
if cuenta < D then
S <= '1';
else
S <= '0';
end if;
end if;
end process;
On statement cuenta:= (cuenta+1) mod 256, the value of cuenta reaches the value of 255 ? , I mean cuenta it is not just 0 all the time ? D is just a value between 0 a 255.
Thanks and I hope someone could help me with this maybe simple question.

Answer 1

I recreated your code with a testbench, if you run this you will be able to tell that cuenta just gets 1 added to it then module devised by 256. I stopped the increment, now it's just a signal driven in.
Getting more information may help actually solve your problem. Hopefully what I have added helps though.
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.std_logic_unsigned.all;
entity cuenta is
port(
clk : in std_logic;
reset : in std_logic;
D : in std_logic_vector(7 downto 0);
cuenta : in std_logic_vector(8 downto 0);
modulo_in : in std_logic_vector(8 downto 0);
S : out std_logic
);
end cuenta;
architecture behav of cuenta is
signal cuenta_q : std_logic_vector(8 downto 0);
begin
process(clk)
begin
if rising_edge(clk) then
if reset = '1' then
cuenta_q <= (others => '0');
S <= '0';
elsif reset = '0' then
cuenta_q <= std_logic_vector(unsigned(cuenta + 1) mod unsigned(modulo_in));
if cuenta_q < D then
S <= '1';
else
S <= '0';
end if;
end if;
end if;
end process;
end behav;
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.std_logic_unsigned.all;
entity tb_cuenta is
end tb_cuenta;
architecture tb of tb_cuenta is
signal clk : std_logic := '1';
signal reset : std_logic := '1';
signal D : std_logic_vector(7 downto 0);
signal cuenta : std_logic_vector(8 downto 0);
signal modulo_in : std_logic_vector(8 downto 0);
signal S : std_logic;
begin
D <= x"F0";
cuenta <= "000100000";
modulo_in <= "100000000";
clk <= not clk after 50 fs;
reset <= '0' after 200 fs;
ceunta_inst : entity work.cuenta
port map(
clk => clk,
reset => reset,
D => D,
cuenta => cuenta,
modulo_in => modulo_in,
S => S
);
end tb;