This question already has answers here:
What is the purpose of .PHONY in a Makefile?
(9 answers)
Closed 7 years ago.
I am using a makefile to run tests. I am not sure about the use of .PHONY. I've read this post: What is the purpose of .PHONY in a makefile?, but still I'm not sure.
I have the following makefile:
```
test:
## Clear console log before we start.
#clear
# Make sure we are not having too much modules.
#npm prune
# Make sure we have the required modules.
#npm install
## Clear the console, so we only see the test results.
#clear
# Run the test.
#./node_modules/.bin/mocha-casperjs test.js --reporter=spec
```
My make test command isn't making any new files. Should I be using the .PHONY: test or not? But even more important, why? (or why not?)
Thank you!
Malcolm Kindermans
Thanks to #Wintermute I got the answer to my question. He commented:
If you removed the tab before them, they'd not show up either -- then they'd be make comments instead of shell comments. Anyway, this question seems to be answered quite extensively behind the link you posted. test should be phony so that touch test; make test doesn't claim that test is up to date. What exactly is still unclear?
So the answer is: "Yes, I need to add test to the .PHONY, because executing the command touch test would break this make command.
Related
This question already has an answer here:
Trying to implement a loop in Makefile target
(1 answer)
Closed 1 year ago.
I am writing a Makefile for a simple projects. The Makefile should produce the README.md of the project which should include a time & date make was run.
Here's what I've got so far:
README.md:dependent_file.sh
now=$(date)
echo "Generated on $now"
clean:
rm *.md
For now, all I want my Makefile to do is append the current date to the README.md
My problem is that I cannot get the actual date-it coms up as blank.
Any help would be appreciated.
Thanks.
Each line of a recipe is executed in a separate shell, so now is not defined in the shell that executes the echo statement. You can use line continuations to join multiple physical lines into a single logical line.
README.md: dependent_file.sh
now=$$(date) \
echo "Generated on $$now"
or use a semicolon to combine both commands on a single line.
README.md: dependent_file.sh
now=$$(date); echo "Generated on $$now"
In both cases, you'll have to use $$ to prevent any expansions from happening in the Makefile before the recipes are executed.
This question already has answers here:
Global environment variables in a shell script
(7 answers)
Closed 5 years ago.
I'm working a small project which needs using OpenMPI to make "mpicc" work.
I made a file make_cmd:
#!/bin/bash
module load OpenMPI
However, after executing ./make_cmd, I was told:
mpicc: command not found
But if I just type on the command line: module load OpenMPI, then mpicc is working.
Why is that? Thanks!
See this answer on neighbouring site.
Because module is an alias/shell function and not a binary program, it's not necessarily available in the non-interactive sub-shell that is created when you run your script. You could probably run source make_cmd though, as that will just run the commands in your current interactive shell. You could ditch the #!/bin/bash line in that case.
This question already has answers here:
Just run single test instead of the whole suite? [duplicate]
(6 answers)
Closed 10 months ago.
I checked documentation and help tutorial. Didn't find answer.
I just want to run a_test.go not all *_test.go.
Is this possible or how?
thanks a lot!
Command Documentation
Command go
Description of testing flags
The following flags are recognized by the 'go test' command and
control the execution of any test:
-run regexp
Run only those tests and examples matching the regular
expression.
To run the tests which satisfy the regex regular expression:
go test -run=regexp
This question already has answers here:
Closed 10 years ago.
Possible Duplicate:
Should I name “makefile” or “Makefile”?
What's the standard convention for make files as far as its capitalization. I've seen both Makefile and makefile. Does it depend on language? Project?
You can use either of them, but conventionally Makefile is preferred over makefile. If you have both Makefile and makefile in the same directory and you just type make then makefile is executed and Makefile is ignored.
It doesn't matter. The make program looks for either one. I personally prefer Makefile since I'm always on Linux and it shows up first in the directory listing since I use lower case on all of my .ccp and .h files.
I believe it is usually capitalized. At least on *nix systems.
Makefile (capitalized) is a standard in Unix world, where file system is case sensitive (i.e. makefile, MAKEFILE and Makefile are all different files). On Windows, it doesn't matter.
This question already has answers here:
What do $< and $# represent in a Makefile?
(2 answers)
Closed 7 years ago.
I am trying to understand a simple command-line string that executes Javac and passes it some simple arguments. The complete command line is:
javac -d $(OUTPATH) -sourcepath $(SOURCEPATH) $<
Everything in this line is straightforward and understandable to me except for the final tokens: $<.
What do these tokens mean?
ADDENDUM: Indeed, the commenters are correct. This line occurs within a makefile. It is obvious to me now, but not when I wrote this question, that a makefile is passed to make and is not a shell script.
Please note: What do $< and $# represent in a Makefile? also discusses this (I did not see it when I looked for previous questions about this).
This looks like something from a makefile, not a command line. In that case, $< expands to the first prerequisite of the current target. That is, the .java file that the .class target depends on.