Generic makefile with files in different directories - makefile

Question

I want develop a generic makefile for the folowing architecture:
30/04/2015 18:10 <REP> .
30/04/2015 18:10 <REP> ..
30/04/2015 18:08 <REP> exe
30/04/2015 17:22 <REP> headers
30/04/2015 17:53 726 makefile.txt
30/04/2015 18:08 <REP> objects
30/04/2015 17:53 <REP> sources
with:
The content of sources
30/04/2015 17:53 <REP> .
30/04/2015 17:53 <REP> ..
30/04/2015 17:22 124 main.c
and the content of headers:
30/04/2015 17:22 <REP> .
30/04/2015 17:22 <REP> ..
30/04/2015 17:22 20 myheader.h
Objects : contents the output object files.
exe: contents the executable
When I put the header files and sources in the same directory, the makefile generates the output. But when I separate them, the make generates an error during dependency.
Here is my current makefile:
SRCDIRS = ../Mydirectory/sources
HDRDIRS = ../Mydirectory/headers
SRCEXTS = .c
HDREXTS = .h
OUTPUT = Output
CC= gcc
SOURCES = $(foreach file,$(SRCDIRS),$(wildcard $(addprefix $(file)/*,.c)))
HEADERS = $(foreach file,$(HDRDIRS),$(wildcard $(addprefix $(file)/*,.h)))
OBJS = $(addsuffix .o, $(basename $(SOURCES)))
DEPS = $(OBJS:.o=.d)
DEP_OPT = -M
DEPEND = $(CC) $(DEP_OPT)
DEPEND.d = $(subst -g ,,$(DEPEND))
COMPILE.c = $(CC) -c -I $(HDRDIRS)
LINK.c = $(CC)
all: $(OUTPUT)
%.d:%.c
[TAB]#echo -n $(dir $<) > $#
#$(DEPEND.d) $< >> $#
objs:$(OBJS)
%.o:%.c
[TAB]$(COMPILE.c) $< -o $#
$(OUTPUT):$(OBJS)
[TAB]$(LINK.c) $(OBJS) -o $#
clean:
[TAB]$(RM) $(OBJS) $(OUTPUT).exe
Update:
The makefile is in Mydirectory.
The output of make -f makefile.txt :
in MS-DOS:
gcc -c -I ../Mydirectory/headers ../Mydirectory/sources/main.c -o ../Mydirectory/sources/main.o
gcc ../Mydirectory/sources/main.o -o Output
And two files are created:
objects/main.o
Mydirectory/Output.exe