I use an atlyse spartan-6 xc6slx45 and I try to do a C code on sdk which permit to read data from a memory of microblaze then do a multiplication of two matrix.I found many tutorials which make the initialisation of the two input matrixes on the C code.Can any one have an idea or a tutorial how to configure the code to read the data input from the memory of the microblaze?
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I can read/write an external sdram using fmc in stm32f429. But working with address and read/write functions is not proper for my purpose. I want to introduce external sdram as if internal sram is clearly extended and whenever I define a big variable it is projected to external sdram automatically.
I checked stm32f4 cubemx repository examples (SDRAM+DATAMEMORY) and searched a lot but it seems this is not straightforward.
Following these steps based on what I found, I get hardfault after system_init.
Defining external sdram address and size in the linker (off-chip ram)
Adding some code in startup_stm32f420xx.s
Defining DATA_IN_ExtSDRAM for initializing sdram before main function
Enabling system clock before main function
My external sdram is connected to SDRAM1 in stm32f429.
What is the correct procedure? Is SystemInit_ExtMemCtl() function implemented correctly? Is any modification needed? Is enabling clock before main function and after system_init needed?
Can anyone tell what is the correct code step by step?
Thanks in advance.
What you are asking for is not really possible.
The internal SRAM and external SDRAM are not contiguous; their addresses are a long way apart and variables cannot simply overflow automatically from one to the other.
The correct steps for using the external memory are exactly as given in the example projects, it would be meaningless to repeat them here.
The work you have to do yourself is to decide which variables go in which memory. You can assign a variable to a section using the gcc section attribute or a similar feature of another compiler. There are examples of this in the STM32Cube package.
I am a newbie here, I used and have my hand on arduino, but now I got task of taking 3000 samples of waveform with 100MSPS with an adc.
As this was impossible with arduino and most of the controller I switch to FPGA,
And bought NUMATO MIMAS v2 (As it has on board 512Mb DDR RAM, which is capable of handling that much fast operation.)
And also bought AD9283 along with it as it has 100MSPS 8bit adc output.
I am using Xilinx ISE, and using Verilog(No specific reason for it).
My PROBLEM is I am unable to interface that inbuilt DDR ram and communicate with it.
Means there are no tutorial to write on that ram and read from it.
So can any one could help me on it?
I think you can read some file from Xilinx about Spartan 6.Like ug416 and ug388 .
Then you can make a Example Design (tutorial) for your board to simulation and communicate with DDR on real board.It is describe in ug416 page 67.You do not code as you creat a MIG IP.It creat a test file automatic.After you simulaion and verify on your board you will familiar with MIG IP.You shoud make sure these questions in this step.Like How many write/read path you will use?How to manage command path?How to addressing?What's the frequency do you need?And so on.
At last you can use MIG by your demand.If you just has only one stream data you will use MIG very easy.Like just use one write path and one read path.
Forgive my English.
I'm working on riscv-sodor and I want to modify the Makefile to generate Verilog. How can I do this task?
Regards,
From the Sodor README (https://github.com/ucb-bar/riscv-sodor):
How can I generate Verilog myself?
You can generate the Verilog code by modifying the Makefile in emulator/common/Makefile.include. In the CHISEL_ARGS variable, change "--backend c" to "--backend v". This will dump a Top.v verilog file of the core and its scratchpad memory (corresponding to the Chisel module named "Top") into the location specified by "--targetDir" in CHISEL_ARGS.
Once you have the Top.v module, you will have to write your own testharness and glue code to talk to Top.v. The main difficulty here is that you need to link the riscv-fesvr to the Sodor core via the HTIF link ("host-target interface"). This allows the fesvr to load a binary into the Sodor core's scratchpad memory, bring the core out of reset, and communicate with the core while it's running to handle any syscalls, error conditions, or test successful/end conditions.
This basically involves porting emulator/*/emulator.cpp to Verilog. I recommend writing a Verilog testharness that interfaces with the existing C++ code (emulator/common/htif_emulator.cc, etc.). emulator/common/htif_main.cc shows an example stub that uses Synopsys's DirectC to interface between a Verilog test-harness and the existing C++ code.
I am working with a SoC Cyclone V board. I want to exchange data between the HPS and FPGA. They share a common RAM, whose address can be seen on Qsys. I would like to Read and write data in this shared Memory, but dont want to use devmem2 every time i do it. I understand that a driver would be much safer. I was thinking of writing a char driver as it is one of the easy drivers to write for the basic read and write operations.
Is there a way to specify the address to be used by the char driver when we build and insert it?
If not, what driver can be written for the this function (to be able to read and write float values on a specific range of virtual address)?
I have found that user io device drivers or block drivers could be good options. But I am new to this area of development and don't know if these are the only options, or are they any more.
I could really use some help in deciding which driver is appropriate, it would be better if it was a char driver where the address can be specified.
Thank you.
I'm using Intel's Pin Tool to do some binary instrumentation, and was wondering if there an API to get the instruction byte code at a given address.
Something like:
instruction = getInstructionatAddr(addr);
where addr is the desired address.
I know the function Instruction (used in many of the simple/manual examples) given by Pin gets the instruction, but I need to know the instructions at other addresses. I perused the web with no avail. Any help would be appreciated!
CHEERS
wondering if there an API to get the instruction byte code at a given
address
Yes, it's possible but in a somewhat contrived way: with PIN you are usually interested in what is executed (or manipulated through the executed instructions), so everything outside the code / data flow is not of any interest for PIN.
PIN is using (and thus ships with) Intel XED which is an instruction encoder / decoder.
In your PIN installation you should have and \extra folder with two sub-directories: xed-ia32 and xed-intel64 (choose the one that suits your architecture). The main include file for XED is xed-interface.h located in the \include folder of the aforementioned directories.
In your Pintool, given any address in the virtual space of your pintooled program, use the PIN_SafeCopy function to read the program memory (and thus bytes at the given address). The advantage of PIN_SafeCopy is that it fails graciously even if it can't read the memory, and can read "shadowed" parts of the memory.
Use XED to decode the instruction bytes for you.
For an example of how to decode an instruction with XED, see the first example program.
As the small example uses an hardcoded buffer (namely itext in the example program), replace this hardcoded buffer with the destination buffer you used in PIN_SafeCopy.
Obviously, you should make sure that the memory you are reading really contains code.
AFAIK, it is not possible to get an INS type (the usual type describing an instruction in PIN) from an arbitrary address as only addresses in the code flow will "generate" an INS type.
As a side note:
I know the function Instruction (used in many of the simple/manual
examples) given by Pin gets the instruction
The Instruction routine used in many PIN example is called an "Instrumentation routine": its name is not relevant in itself.
Pin_SafeCopy may help you. This API could copy memory content from the address space of target process to one specified buffer.