I am just starting to learn VHDL and thought I would go threw the book examples and put them into the compiler and then attach a constraints file and try running it on the CPLD board that I got for the class. Problem being that once all the code is done and the compiler finishes and I program it onto the board I am getting no response from the board from my input.
I am now wondering if I made a mistake in the VHDL code that was copped from the book, I am not finding any difference from the book but I was hopping another with more experience could look it over and point out if I made a mistake.
--Truth Table page 193
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity TruthTable is
Port (
a,b,c : in bit;
y : out bit);
end TruthTable;
architecture truth of TruthTable is
Signal in_bits : Bit_vector (2 downto 0);
begin
in_bits <= a & b & c;
with in_bits select
y <= '0' when "000",
'0' when "001",
'0' when "010",
'1' when "011",
'1' when "100",
'0' when "101",
'1' when "110",
'1' when "111";
end truth;
Your code is fine. I would guess the problem resides in the mapping between the VHDL pins a, b, c and d and the board's CPLD's pinout.
I advise you to revise the synthesis and program processes, and to double-check your pin mapping.
Related
Can someone please help me understand what my syntax error is in this code?
Also, is there an IDE for VHDL that will highlight bad syntax and errors?
I am taking a graduate level HDL class online, have never written VHDL or other RTL languages before, and the prerecorded lectures aren't the greatest. Can someone please also recommend some resources/reading material for me to look over?
I am currently using ModelSim on a student license, FYI.
The error code I keep getting is...
"AAC2M1P4.vhd(47): near "EOF": syntax error"
library ieee;
use ieee.std_logic_1164.all;
entity Majority is port (
A, B, C: in std_logic;
Y: out std_logic);
end Majority;
architecture behavioral of Majority is
signal s: std_logic_vector (3 downto 0);
begin
s(0) <= A and B and C;
s(1) <= (not A) and B and C;
s(2) <= A and (not B) and C;
s(3) <= A and B and (not C);
Y <= s(0) or s(1) or s(2) or s(3);
end behavioral;
I'm new in this world.
Actually, I'm learning VHDL. I've written the below code:
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity Problems is
port(
S : in std_logic;
D : in std_logic;
CLK : in std_logic;
R : in std_logic;
Q : out std_logic;
Q_n : out std_logic
);
end Problems;
architecture Behavioral of Problems is
signal t_tmp1 : std_logic;
begin
DFF: process (S,R,D,CLK)
begin
if (S = '0' and R = '0') then
t_tmp1 <= not t_tmp1;
elsif (S = '0' and R = '1') then
t_tmp1 <= '1';
elsif (S = '1' and R = '0') then
t_tmp1 <= '0';
elsif (rising_edge(CLK)) then
t_tmp1 <= D;
end if;
end process DFF;
Q <= t_tmp1;
Q_n <= not t_tmp1;
end Behavioral;
When I synthesized appear me the below warnings:
WARNING:HDLCompiler:92 - "/home/joseph/ISEProjects/Exercise_BasicMemoryElements/Problems.vhd" Line 41: t_tmp1 should be on the sensitivity list of the process
WARNING:Xst:3002 - This design contains one or more registers/latches that are directly
incompatible with the Spartan6 architecture. The two primary causes of this is
either a register or latch described with both an asynchronous set and
asynchronous reset or a register or latch described with an asynchronous
set or reset which however has an initialization value of the opposite
polarity (i.e. asynchronous reset with an initialization value of 1).
The simulation works well.
I want to know why the warnings and what do I have to learn to solve problems like this.
Regards,
Joseph Peña.
If you were to read through Spartan-6 Libraries Guide for Schematic Designs you'd find a D flip flop with both an asynchronous Preset and asynchronous Clear isn't provided by Spartan 6 (or later device families for that matter).
Your if statement's first condition statement's behavior doesn't appear to represent what would happen if both a reset and a set were TRUE at the same time either. A distinction between what you can simulate and what you can technology map through synthesize.
In Spartan-3e for instance the reset would override the set:
Constraints on the synthesis eligible subset of the VHDL language for mapping into Register Transfer Logic elements in a target technology are found in IEEE Std 1076.6-2004, now rescinded, and can be found for Xilinx either in the ISE XST User Guide or Vivado Design Suite User Guide Synthesis (ug901).
The ability to map a VHDL description is predicated on having a supported target for the device family.
in reference to this post How to write to two output ports from inside architecture in VHDL? I made a VHDL module using the same concept as decribed in one of its answers.
His code:
entity HIER is
port (
IN1 : in bit;
OUT1, OUT2 : out bit);
end hier;
architecture HIER_IMPL of HIER is
signal temp : bit;
component BUF1 is
port (a : in bit; o : out bit);
end component;
begin
BUF2 : BUF1 port map (a => IN1, o => temp);
OUT1 <= temp;
OUT2 <= temp;
end HIER_IMPL;
His generated RTL(using xilinx 9.1i)
I made a D flip flop using the same concept of signal to drive output ports
my code:
entity dfff is
Port ( D : in STD_LOGIC;
clk : in STD_LOGIC;
Q : out STD_LOGIC;
Qbar : out STD_LOGIC);
end dfff;
architecture Behavioral of dfff is
component nand_2 is
port(A:in std_logic;
B:in std_logic;
C:out std_logic);
end component;
component not_1 is
port(A:in std_logic;
B:out std_logic);
end component;
signal Z : std_logic_vector(4 downto 0);
begin
n1 : not_1 port map (D,z(0));
n2 : nand_2 port map(D,clk,z(1));
n3 : nand_2 port map(z(0),clk,z(2));
n4 : nand_2 port map(z(1),z(3),z(4));
n5 : nand_2 port map(z(2),z(4),z(3));
Q<=z(4);
Qbar<=z(3);
end Behavioral;
my generated RTL(using xilinx 9.1i):
Now MY question is that why My output ports Q and Qbar not visible in the RTL while his OUT1 and OUT2 are?
I am a beginner in this field.
Works fine in ISE14.4. I remember old versions of RTL Viewer being practically unusable.
When I first started writing VHDL I also tried writing a FF in discrete gates, AFAIR it didn't go too well.
You should be writing to your platform (in this case probably some Xilinx chip), knowing what it is and does.
This will also help you when you get on in your training, FPGAs and CPLDs are not great arrays of AND and OR gates, they are great arrays of lookup tables, so the chance of an implementation of a FF in an FPGA turning out well is slim to none.
Regarding your actual question, I'd first make sure I actually have my outputs set to go somewhere. The synthesizer tries very hard not to include superfluous circuitry, so if your result doesn't end in anything, it might get optimized away (even though that should surely also optimize away the circuitry that you did get).
Also as mentioned, try updating your tools, 14.7 is a far stretch newer than 9.1 and that is even from October 2013.
Please note, this is a study question.
I have to describe a simple d-latch in vhdl, and then synthesize it. The problem is that it is a "unary" d-latch, and its single input is mapped directly to its outputs (Q and nQ). You can imagine it as a classical async d-latch, where clk signal is always high. This is useless element in logic, and xilinx synthesizer in most cases gives an empty technology schema. But the reason to keep this element is, for example, creating hardware "watermarks", which present on the schema, but don't affect its logic.
I came up with the following code:
entity dLatch is
port(
d: in std_logic;
q: out std_logic);
end dLatch;
architecture dLatch_beh of dLatch is
signal o: std_logic;
begin
latch: process(d)
begin
if d = '1' then
o <= '1';
elsif d = '0' then
o <= '0';
end if;
end process;
q <= o;
end;
This code produce the following technology schema
link
But when I try to add nQ out port, I gain duplication of latch
entity dLatch is
port(
d: in std_logic;
q, nq: out std_logic);
end dLatch;
architecture dLatch_beh of dLatch is
signal o: std_logic;
begin
latch: process(d)
begin
if d = '1' then
o <= '1';
elsif d = '0' then
o <= '0';
end if;
end process;
q <= o;
nq <= not o;
end;
Technology schema: link
I don't understand, why I am getting two completely equal latches here. I expected only one additional 'not' gate.
So my question is how to avoid the duplication of latches, or maybe some other way to solve this problem.
I use Xilinx ISE Web Pack 14.6 for synthesis.
UPD The solution is to set synthesizer's flag -register_duplication to false.
You're not getting any latches at all. You are looking at the Technology view, so it is showing you what Xilinx components it mapped into. You should be looking at RTL view instead first of all.
Secondly, latches are BAD as your professor probably made you aware. He even says in the description that the view will be blank because the tools will not generate a latch for you. They don't exist in the fabric.
The solution is to set synthesizer's flag -register_duplication to false.
I am writing a RS232 module for my Nexys2 board. I am currently having issues with my baud rate controller which I want to set to 19200.
For this I am using a Mod-M counter, after many ISim simulations the problem with my code is in the mod-m counter as it is not producing any ticks.
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity baud_rate is
generic (
N: integer := 8;
M: integer :=163);
Port (clk, reset : in STD_LOGIC;
tick : out STD_LOGIC;
q : out STD_LOGIC_VECTOR(N-1 downto 0));
end baud_rate;
architecture Behavioral of baud_rate is
signal r_reg : unsigned(N-1 downto 0);
signal r_next : unsigned(N-1 downto 0);
begin
process(clk,reset)
begin
if (reset ='1') then
r_reg <= (others=>'0');
elsif(clk'event and clk='1') then
r_reg <= r_next;
end if;
end process;
r_next <= (others =>'0') when r_reg=(M-1) else r_reg+1;
tick <='1' when r_reg=(M-1) else '0';
q <= std_logic_vector(r_reg);
end Behavioral;
I have tested and all the clk inputs and run fine and the issue seems to be with the r_reg and r_next registers. In ISim when outputing either of these on q I get UUUUUUUU, so it seems they are not generating signal. From this i can infer that the two r_reg and r_next registers aren't being created or storing values, is there an issue when using unsigned?
To make triple sure I have even copied the mod-m counter from the book FPGA Prototyping with VHDL (which is the code shown) BUT still this does not work and q output is UUUUUUUU.
If there are any better ways of creating a baud rate from the nexys2 50mz clock that would also be appreciated!
Cheers
Frankly I am horrified if people are expected to learn VHDL from a book where examples like this are presented. I know the author has a similar book on Verilog : do people end up thinking VHDL is just a more verbose Verilog?
Specific criticisms (actually 7,8 are more observations):
1) Spurious type conversions.
Q represents an unsigned number. So make it unsigned!
The baud generator isn't the only thing in your FPGA so Q isn't likely to be an off-chip port. There are good arguments for making top level, off-chip ports std_logic_vector but even that isn't compulsory. However, if your customer's specification or coding style insists on spurious type conversions on ports; follow it.
2) the DRY principle:
package CPU_types is
subtype baud_count is unsigned(7 downto 0);
end CPU_types;
Spot the simplification in maintenance.
If you are using a subtype in several places, put it in a package; the universal code reuse tool.
3) Indentation, formatting. (I recognise that may have become garbled by editor settings). It adds to the brain load reading it. What I've done here isn't The One Way though.
4) Spurious brackets round logical expressions. Harmless, but look like crutches for C programmers.
5) Antique clk'event style. Next year, the rising_edge function will be old enough to drink (in America. In Britain it's been getting plastered every Saturday night for a couple of years now...)
6) The "two process" style with r_reg and r_next. Does he also write state machines with a separate combinational process on next_state? Given this, I'm guessing so. Single process state machines are easier, smaller (to write : they don't generate smaller hardware) and safer.
7) I cheated and my tick is one cycle later than in the original. If that is critical, restore the external "tick" assignment. I also made it synchronous vhich will help performance. Some people would prefer tick <= '0' in an else clause; however the default assignment I used is safe, and prevents a lot of mistakes (and unnecessary else clauses) in larger designs.
8) The assignment to Q can be brought into the process too; if you made r_reg a process variable you'd have to. There is room for other variations and preferences.
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
use CPU_types.all;
entity baud_rate is
generic (
M: integer := 163);
Port (
clk, reset : in STD_LOGIC;
tick : out STD_LOGIC;
q : out baud_count);
end baud_rate;
architecture Behavioral of baud_rate is
signal r_reg : baud_count;
begin
process(clk,reset)
begin
if reset ='1' then
r_reg <= (others=>'0');
elsif rising_edge(clk) then
tick <= 0;
r_reg <= r_reg+1;
if r_reg = M then
tick <= '1';
r_reg <= (others=>'0');
end if;
end if;
end process;
-- tick <='1' when r_reg = M-1 else '0';
-- or simpler, when r_reg = 0
q <= r_reg;
end Behavioral;