Can someone please help me understand what my syntax error is in this code?
Also, is there an IDE for VHDL that will highlight bad syntax and errors?
I am taking a graduate level HDL class online, have never written VHDL or other RTL languages before, and the prerecorded lectures aren't the greatest. Can someone please also recommend some resources/reading material for me to look over?
I am currently using ModelSim on a student license, FYI.
The error code I keep getting is...
"AAC2M1P4.vhd(47): near "EOF": syntax error"
library ieee;
use ieee.std_logic_1164.all;
entity Majority is port (
A, B, C: in std_logic;
Y: out std_logic);
end Majority;
architecture behavioral of Majority is
signal s: std_logic_vector (3 downto 0);
begin
s(0) <= A and B and C;
s(1) <= (not A) and B and C;
s(2) <= A and (not B) and C;
s(3) <= A and B and (not C);
Y <= s(0) or s(1) or s(2) or s(3);
end behavioral;
Related
So, I have to create a generic N-bit adder with carry in and carry out.
I have made two fully working architectures so far, one using the generate function and one using the rtl description as follows:
entity:
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity adder_n is
generic (N: integer:=8);
port (
a,b: in std_logic_vector(0 to N-1);
cin: in std_logic;
s: out std_logic_vector(0 to N-1);
cout: out std_logic);
end adder_n;
architectures 1 and 2:
--STRUCT
architecture struct of adder_n is
component f_adder
port (
a,b,cin: in std_logic;
s,cout: out std_logic);
end component;
signal c: std_logic_vector(0 to N);
begin
c(0)<=cin;
cout<=c(N);
adders: for k in 0 to N-1 generate
A1: f_adder port map(a(k),b(k),c(k),s(k),c(k+1));
end generate adders;
end struct;
--END STRUCT
architecture rtl of adder_n is
signal c: std_logic_vector(1 to N);
begin
s<=(a xor b) xor (cin&c(1 to N-1));
c<=((a or b) and (cin&c(1 to N-1))) or (a and b);
cout<=c(N);
end rtl;
Now, my problem is in the third architecture where I'm trying to infer the adder. Even though the following architecture I created compiles just fine, when I try to simulate it, I get a simulation error (on Modelsim), which I have attached at the end of this post.
I'm guessing there's something wrong with the numeric_std definitions. I am trying to avoid the arith library and I'm still trying to get used to the IEEE standard.
Any ideas are welcomed!! Thank you!
Inference arch:
--INFERENCE
architecture inference of adder_n is
signal tmp: std_logic_vector(0 to N);
signal atmp, btmp, ctmp, add_all : integer :=0;
signal cin_usgn: std_logic_vector(0 downto 0);
signal U: unsigned(0 to N);
begin
atmp <= to_integer(unsigned(a));
btmp <= to_integer(unsigned(b));
cin_usgn(0) <= cin;
ctmp <= to_integer(unsigned(cin_usgn));
add_all <= (atmp + btmp + ctmp);
U <= to_unsigned(add_all,N);
tmp <= std_logic_vector(U);
s <= tmp(0 to N-1);
cout <= tmp(N);
end inference;
-- END
Simulation error:
# Cannot continue because of fatal error.
# HDL call sequence:
# Stopped at C:/altera/14.1/modelsim_ase/test1_simon/adder_inference.vhd 58 Architecture inference
The length of U is N+1 (0 to N)
Changing
U <= to_unsigned(add_all,N);
To
U <= to_unsigned(add_all,N+1);
Will prevent a length mismatch between the left hand side and right hand side of the signal assignment in architecture inference of adder_n.
The passed parameter to to_unsigned specifies the length.
I am just starting to learn VHDL and thought I would go threw the book examples and put them into the compiler and then attach a constraints file and try running it on the CPLD board that I got for the class. Problem being that once all the code is done and the compiler finishes and I program it onto the board I am getting no response from the board from my input.
I am now wondering if I made a mistake in the VHDL code that was copped from the book, I am not finding any difference from the book but I was hopping another with more experience could look it over and point out if I made a mistake.
--Truth Table page 193
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity TruthTable is
Port (
a,b,c : in bit;
y : out bit);
end TruthTable;
architecture truth of TruthTable is
Signal in_bits : Bit_vector (2 downto 0);
begin
in_bits <= a & b & c;
with in_bits select
y <= '0' when "000",
'0' when "001",
'0' when "010",
'1' when "011",
'1' when "100",
'0' when "101",
'1' when "110",
'1' when "111";
end truth;
Your code is fine. I would guess the problem resides in the mapping between the VHDL pins a, b, c and d and the board's CPLD's pinout.
I advise you to revise the synthesis and program processes, and to double-check your pin mapping.
Please note, this is a study question.
I have to describe a simple d-latch in vhdl, and then synthesize it. The problem is that it is a "unary" d-latch, and its single input is mapped directly to its outputs (Q and nQ). You can imagine it as a classical async d-latch, where clk signal is always high. This is useless element in logic, and xilinx synthesizer in most cases gives an empty technology schema. But the reason to keep this element is, for example, creating hardware "watermarks", which present on the schema, but don't affect its logic.
I came up with the following code:
entity dLatch is
port(
d: in std_logic;
q: out std_logic);
end dLatch;
architecture dLatch_beh of dLatch is
signal o: std_logic;
begin
latch: process(d)
begin
if d = '1' then
o <= '1';
elsif d = '0' then
o <= '0';
end if;
end process;
q <= o;
end;
This code produce the following technology schema
link
But when I try to add nQ out port, I gain duplication of latch
entity dLatch is
port(
d: in std_logic;
q, nq: out std_logic);
end dLatch;
architecture dLatch_beh of dLatch is
signal o: std_logic;
begin
latch: process(d)
begin
if d = '1' then
o <= '1';
elsif d = '0' then
o <= '0';
end if;
end process;
q <= o;
nq <= not o;
end;
Technology schema: link
I don't understand, why I am getting two completely equal latches here. I expected only one additional 'not' gate.
So my question is how to avoid the duplication of latches, or maybe some other way to solve this problem.
I use Xilinx ISE Web Pack 14.6 for synthesis.
UPD The solution is to set synthesizer's flag -register_duplication to false.
You're not getting any latches at all. You are looking at the Technology view, so it is showing you what Xilinx components it mapped into. You should be looking at RTL view instead first of all.
Secondly, latches are BAD as your professor probably made you aware. He even says in the description that the view will be blank because the tools will not generate a latch for you. They don't exist in the fabric.
The solution is to set synthesizer's flag -register_duplication to false.
I am trying to make a dataflow design for a comparator in VHDL. It compiles and simulates fine in Xilinx, but I have to use Cadence/NCLaunch. When I copied the same code to gedit and ran it, it gives an error about a semicolon.
my code is :
library ieee;
use ieee.std_logic_1164.all;
-----------------------------------------------------
entity Comparator is
port( A: in std_logic_vector (3 downto 0);
B: in std_logic_vector (3 downto 0);
AeqB: out std_logic;
AltB: out std_logic;
AgtB: out std_logic);
end Comparator;
architecture dataflow of Comparator is
signal AeB : std_logic;
signal AlB : std_logic;
signal AgB : std_logic;
signal i : std_logic_vector (3 downto 0);
signal j : std_logic_vector (3 downto 0);
begin
B1: BLOCK BEGIN
AeB <= i(3) AND i(2) AND i(1) and i(0);
AgB <= j(3) or j(2) or j(1) or j(0);
AlB <= AeB nor AgB;
END BLOCK B1;
B2: BLOCK BEGIN
i <= a xnor b;
END BLOCK B2;
B3: BLOCK BEGIN
j(3) <= (not b(3)) and a(3);
j(2) <= i(3) and not b(2) and a(2);
j(1) <= i(3) and i(2) and not b(1) and a(1);
j(0) <= i(3) and i(2) and i(1) and not b(0) and a(0);
END BLOCK B3;
B4: BLOCK BEGIN
AeqB <= AeB;
AltB <= AlB;
AgTB <= AgB;
END BLOCK B4;
end dataflow;
...and the error I get is:
i <= a xnor b;
|
ncvhdl_p: *E,EXPSMI (/ugrad/syedhuq/ECE425/Lab2/Comparator.vhd,29|11): expecting a semicolon (';') [9.5.1].
As far as I can tell, I have a semicolon there...also if I replace the statement with four individual statements like
i(n) <= a(n) xnor b(n); //[n = 1, 2, 3, 4],
i get the same error 4 times. Can anyone help me out with this??
Also, it compiles fine in Synopsys (VCSMX) and so does the testbench file, but during the linking process it tells me :
Design unit 'COMPARATOR(BEHAVE)' from library '.' cannot be opened for
reading.
Possible causes:
[1] Incorrect logical to physical mapping in synopsys_sim.setup file.
[2] Intermediate file generation was prematurely terminated during analysis.
Reanalyze the design unit and resolve any errors that occur during analysis.
the relevant line from the testbench code is:
for x1: Comparator use entity work.Comparator(Behave);
I'm not familiar with Cadence/NCLaunch, but knowing your code analyzes correctly in an IEEE 1076-1993 compliant tool, and noting where error is (you indicated character position 11 in line 29, noting it appears to be character position 17), I'd say off hand it either doesn't have "xnor" un-commented in package std_logic_1164 (both the specification and the body), or it's a VHDL87 compliant tool, or there's some missing tool set or command line argument to use use the proper std_logic_1164 package.
In the distributed source for std_logic_1164, available from
http://standards.ieee.org/downloads/1076/1076.2-1996/
-- --------------------------------------------------------------------
-- version | mod. date:|
-- v4.200 | 01/02/92 |
-- --------------------------------------------------------------------
You'll find that xnor is commented out by default, when after VHDL92 (-1993, don't ask) was approved it was supposed to be un-commented.
-- -----------------------------------------------------------------------
-- Note : The declaration and implementation of the "xnor" function is
-- specifically commented until at which time the VHDL language has been
-- officially adopted as containing such a function. At such a point,
-- the following comments may be removed along with this notice without
-- further "official" ballotting of this std_logic_1164 package. It is
-- the intent of this effort to provide such a function once it becomes
-- available in the VHDL standard.
-- -----------------------------------------------------------------------
-- function "xnor" ( l, r : std_logic_vector ) return std_logic_vector;
-- function "xnor" ( l, r : std_ulogic_vector ) return std_ulogic_vector;
9.5.1 refers to Conditional signal assigns in IEEE=1076-1993.
The analyzer is acting like it doesn't recognize xnor as a operator and if you look in -1993 7.2.1 Logical operators:
The logical operators and, or, nand, nor,xor, xnor, and not are
defined for predefined types BIT and BOOLEAN. They are also defined
for any one-dimensional array type whose element type is BIT or
BOOLEAN.
Which tells us in an IEEE 1076-1993 compliant tool the declarations for xnor would come from the std_logic_1164 package.
I had a quick gander through some NCSIM, etc. online user guides and tutorials and didn't see anything relating to the problem. It's likely the std_logic_1164 package hadn't had xnor un-commented in both the declaration and body.
The issue may be the the providence (age) or the particular tool copy you are using and may require sysadmin help to correct. In the mean time you can either write your own xnor function (shown), if running into any difficulties try and use not( a xor b) instead.
architecture dataflow of Comparator is
function "xnor" ( l : std_logic; r : std_logic ) return ux01 is
begin
return not (l xor r);
end "xnor";
signal AeB : std_logic;
signal AlB : std_logic;
signal AgB : std_logic;
signal i : std_logic_vector (3 downto 0);
signal j : std_logic_vector (3 downto 0);
begin
Also see Weird XNOR behaviour in VHDL
I'm trying to design a 32bit binary serial adder in VHDL, using a structural description. The adder should make use of a full adder and a d-latch. The way I see it is:
Full adder:
architecture Behavioral of FullAdder is
begin
s <= (x xor y) xor cin;
cout <= (x and y) or (y and cin) or (x and cin);
end Behavioral;
D-Latch:
architecture Behavioral of dLatch is
begin
state: process(clk)
begin
if(clk'event and clk = '1') then
q <= d;
end if;
end process;
end Behavioral;
Serial adder:
add: process ( clk )
variable count : integer range 0 to 31;
variable aux : STD_LOGIC;
variable aux2 : STD_LOGIC;
begin
if(clk'event and clk = '1') then
fa: FullAdder port map(x(count), y(count), aux, s(count), aux2);
dl: dLatch port map(clock, aux2, aux);
count := count + 1;
end if;
end process;
However, it doesn't seem to work.
Also, what would be the simplest way to pipeline the serial adder?
"It doesn't seem to work" is pretty general, but one problem I see is that you are trying to instantiate the component fa: FullAdder within a process. Think about what component instantiation means in hardware, and you will realize that it makes no sense to instantiate the module on the rising_edge of clk...
Move the instantiation out of the process, and it should at least remove the syntax error you should be seeing ("Illegal sequential statement." in ModelSim).
For pipelining the serial adder, the best way is to connect the adders and d flip-flops one after the other. So, you would have the cout of the first adder be the input of a flip-flop. The output of that flip-flop will be the cin of the next adder and so on. Be careful though, because you will also have to pipeline the s of each adder, as well as each bit of the input, by essentially putting several d flip-flops in a row to copy them through the various pipeline stages.