In my VHDL project, my input is going to be extracted from a text file containing n bits of 1's and 0's. I am trying to make it as general as possible. I am familiar with how to read and write on a text file using test-bench, but I don't know how to check its length.
My code normally takes 64 bit as input, pass them through all the blocks and generate an output. If the remaining bits length is less than 64 then it passes through a specific block.
Let's say the text file contains 1000 bits. 15 x 64 = 960. 960 bits will pass through all blocks, the remaining 40 will pass by a specific block. This looks straight forward but in order for me to do such operations i need to know the length of the text file. If anyone can help that would be very beneficial.
The VHDL data structure length should be considered, not the file length since that is implementation specific and not VHDL specified.
If the bits are in one long string that is to be chopped up into 64-bit pieces with a remainder, then the entire string can be read into a VHDL line type, and reading from that line to a std_logic_vector type can then depend on the remaining bits (characters) in the line.
Below is a code example doing so:
library ieee;
use std.textio.all;
use ieee.std_logic_textio.all; -- Synopsys package; required for VHDL-2002 only
architecture syn of tb is
begin
process is
variable myl_v : line;
file txt_file : text;
variable slv_v : std_logic_vector(63 downto 0);
begin
file_open(txt_file, "input.txt", read_mode);
readline(txt_file, myl_v);
while myl_v'length > 0 loop
if myl_v'length >= slv_v'length then -- Full slv_v
report "Full...: " & myl_v.all(1 to slv_v'length);
read(myl_v, slv_v);
else -- Reduced slv_v
report "Reduced: " & myl_v.all(1 to myl_v'length);
read(myl_v, slv_v(myl_v'length - 1 downto 0)); -- Place reduced at LSBs
end if;
end loop;
file_close(txt_file);
wait;
end process;
end architecture;
Btw, to answer the question of "length of an input text file", then the length in characters can be determined by reading as many characters from the file as possible, for example with code like:
impure function file_length_in_characters(filename : string) return natural is
type char_file_t is file of character;
file char_file : char_file_t;
variable char_v : character;
variable res_v : natural;
begin
res_v := 0;
file_open(char_file, filename, read_mode);
while not endfile(char_file) loop
read(char_file, char_v);
res_v := res_v + 1;
end loop;
file_close(char_file);
return res_v;
end function;
Related
the temp variable is storing data out of its range. The range is used to store the maximum final value but it is holding the previous value and goes on incrementing. The functionality of for loop which is condition based is not satisfingenter image description here
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity counter is
Port (clk,rst:in std_logic;
o:out integer range 0 to 15
);
end counter;
architecture Behavioral of counter is
signal temp2:integer range 1 to 15:=0;
begin
process(clk) is
begin
if rising_edge(clk) then
if rst='1' then
temp2<=0;
else
for i in 1 to 15
loop
temp2<=temp2+1;
end loop;
end if;
end if;
end process;
o<=temp2;
end Behavioral;
Range puts a constraint on an object (here the signal temp2) that says it is illegal, and hence, fail if this object receives a value that is outside of the range.
Your code then must take the actions (such as mod) to make this so.
Since your code assigns the value 0, I am assuming that you need to update your declaration as follows:
signal temp : integer range 0 to 15 ;
. . .
temp2<= (temp2+1) mod 16;
I would like to separate my data with new line character in an output file, but the following codes result in error "can't resolve overload for procedure call":
write(out_line, "\n");
write(out_line, "");
write(out_line, '');
An example code how I want to use it:
ENTITY writer IS
PORT ( clk : IN STD_LOGIC := '0'; start : IN STD_LOGIC := '0');
END ENTITY;
ARCHITECTURE arch OF writer IS
SIGNAL vect : STD_LOGIC_VECTOR (2 downto 0) := "000";
TYPE state_type IS (init, write_file);
SIGNAL state : state_type := init;
BEGIN
PROCESS (clk, start)
FILE out_file : text;
VARIABLE out_line : line;
BEGIN
IF rising_edge(clk) THEN
CASE state IS
WHEN init =>
IF start = '1' THEN
state <= write_file;
ELSE
state <= init;
END IF;
WHEN write_file =>
state => init;
FOR i IN 0 TO 10 LOOP
write(out_line, vect);
writeline(out_file, out_line);
-- write(out_line, "\n"); <--
-- write(out_line, ""); <--
-- write(out_line, ''); <-- None of these work
writeline(out_file, out_line);
END LOOP;
END CASE;
END IF;
END PROCESS;
END ARCHITECTURE;
So I would like to know, is it possible in VHDL? If yes, how?
The following will consistently give you a single blank line:
write(out_line, string'(""));
writeline(out_file, out_line);
I suspect what #Dani posted may be tool dependent. For example while on one popular simulator, the following produces one line feed:
write(out_line, LF);
writeline(out_file, out_line);
However when I add a space after the LF, I get two lines:
write(out_line, LF & ' ');
writeline(out_file, out_line);
Creating a minimal, complete and verifiable example from the question's incomplete sample code:
library ieee; -- ADDED
use ieee.std_logic_1164.all; -- ADDED
use std.textio.all; -- ADDED
-- use ieee.std_logic_textio.all; -- ADDED for revisions earlier than -2008
ENTITY writer IS
-- PORT ( clk : IN STD_LOGIC := '0'; start : IN STD_LOGIC := '0');
END ENTITY;
ARCHITECTURE arch OF writer IS
SIGNAL vect : STD_LOGIC_VECTOR (2 downto 0) := "000";
-- TYPE state_type IS (init, write_file);
-- SIGNAL state : state_type := init;
BEGIN
PROCESS -- (clk, start)
FILE out_file : text;
VARIABLE out_line : line;
BEGIN
file_open(out_file, "some_file", WRITE_MODE); -- ADDED
-- IF rising_edge(clk) THEN
-- CASE state IS
-- WHEN init =>
-- IF start = '1' THEN
-- state <= write_file;
-- ELSE
-- state <= init;
-- END IF;
-- WHEN write_file =>
-- state => init;
FOR i IN 0 TO 10 LOOP
write(out_line, vect);
writeline(out_file, out_line);
-- write(out_line, "\n"); <--
-- write(out_line, ""); <--
-- write(out_line, ''); <-- None of these work
writeline(out_file, out_line);
END LOOP;
-- END CASE;
-- END IF;
wait; -- ADDED
END PROCESS;
END ARCHITECTURE;
demonstrates a way to get a blank line in the output:
some_file contents:
000
000
000
000
000
000
000
000
000
000
000
The second writeline procedure call produces an empty line without an intervening write procedure call.
Why is seen in IEEE Std 1076-2008 16.4 Package TEXTIO:
Procedures READLINE, WRITELINE, and TEE declared in package TEXTIO read and write entire lines of a file of type TEXT. Procedure READLINE causes the next line to be read from the file and returns as the value of parameter L an access value that designates an object representing that line. If parameter L contains a non-null access value at the start of the call, the procedure may deallocate the object designated by that value. The representation of the line does not contain the representation of the end of the line. It is an error if the file specified in a call to READLINE is not open or, if open, the file has an access mode other than read-only (see 5.5.2). Procedures WRITELINE and TEE each cause the current line designated by parameter L to be written to the file and returns with the value of parameter L designating a null string. Procedure TEE additionally causes the current line to be written to the file OUTPUT. If parameter L contains a null access value at the start of the call, then a null string is written to the file or files. If parameter L contains a non-null access value at the start of the call, the procedures may deallocate the object designated by that value. It is an error if the file specified in a call to WRITELINE or TEE is not open or, if open, the file has an access mode other than write-only.
The language does not define the representation of the end of a line. An implementation shall allow all possible values of types CHARACTER and STRING to be written to a file. However, as an implementation is permitted to use certain values of types CHARACTER and STRING as line delimiters, it might not be possible to read these values from a TEXT file.
A line feed (LF) format effector occurring as an element of a string written to a file of type TEXT, either using procedure WRITELINE or TEE, or using the WRITE operation implicitly defined for the type TEXT, is interpreted by the implementation as signifying the end of a line. The implementation shall transform the LF into the implementation-defined representation of the end of a line.
...
For each WRITE, OWRITE, and HWRITE procedure, after data is appended to the string value designated by the parameter L, L designates the entire line. The procedure may modify the value of the object designated by the parameter L at the start of the call or may deallocate the object.
If deallocation occurs out_line will have a value of null after a writeline call and a null string is written in the immediately following writeline call which also provides an end of line.
If the object value accessed by out_line is a null array (having no elements, 5.3.2.2 Index constraints and discrete ranges, a null string) the immediately following writeline call will result in an end of line being written to the file.
In essence your code example already contains one of these methods for writing a blank line, which depends on whether deallocation is used conditionally (may).
Variants of allocate() and free() can be relatively expensive in terms of execution time and when the size of the allocated object and it's element size is known a smaller 'allocated' object can be written to the same object space saving simulation time. The simulation kernel representation of an array object can have bounds separate from the array value, deallocation and re-allocation can be reserved for when the object size is larger than the previously allocated size or an explicit deallocate call occurs.
There's also a requirement that an implementation translate an LF character to an end of line in a write to a file. This is the other mechanism that allows you to write an LF character as the last or only character to a line and get a following blank line.
You could also explicitly write a null string to out_line
write(out_line, string'(""));
prior to the second writeline call. The qualified expression provides the type of the string literal unlike the attempt commented out in the original question where the type of the string literal can't be determined. See 9.3.2 Literals "... The type of a string or bit string literal shall be determinable solely from the context in which the literal appears, excluding the literal itself but using the fact that the type of the literal shall be a one-dimensional array of a character type. ...". The procedure write would be ambiguous in this context, failing overload resolution (12.5 The context of overload resolution).
Finally after a lot of searching and trying I found that the following code works:
write(out_line, lf);
writeline(out_file, out_line);
I found that write(out_line, cr); does the same thing, and write(out_line, nul); adds ' ' character between the outputs.
Edit: Okay I am able to re read the first line. Problem now is that it keeps repeat the first line only and doesn't move on to the next line. From all the loops I see, it suppose to look like it would work.
I am working on a program for simulation purposes which reads hex data byte by byte from a text file and outputs it in a 1 bit per clock cycle.
I would like to reuse the same line multiple times after reading it before moving on to another read line. For testing purposes of whether it could re read the same line I used
inline2 := new string'(inline.all);
and copied and paste the same code below and changing some of the read variables. Which worked I was able to read the same line twice, however I am planning to use a while loop to implement it for quite a number of readings and I have trouble doing so.
I was whether is it possible or did I make a mistake again.
Basically my goal is for text file first line containing AA BB CC, 2nd line containing DD EE FF.
Setting
signal Seqcount: integer = := 0
Using a (while Seqcount loop of <3) I would like the output to be
AA BB CC
AA BB CC
AA BB CC
DD EE FF
DD EE FF
DD EE FF
I tried adding
While (Seqcount <3) loop
inline := new string'(inline.all);
followed by my read codes. However, it only read the data once and stopped. Without looping again.
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE IEEE.std_logic_textio.all;
LIBRARY STD;
USE STD.textio.all;
USE IEEE.std_logic_unsigned.all;
USE IEEE.numeric_std.all;
entity readtext is
port (
IN_SRX2_BPSKDAT1: OUT std_logic
);
end readtext;
ARCHITECTURE arch_name OF readtext IS
signal readdatainput : std_logic_vector (7 downto 0);
signal linenumber : integer:=0;
signal Bitreading : std_logic;
signal Bitcount : integer := 0;
signal SeqCount: integer := 1;
BEGIN
clock <= not (clock) after 0.5 ms;
reading:
process
file infile : text is in "A.txt"; --A.txt contains AA 00 AA on the first line followed by BB 11 BB on next line.
variable inline : line; --line number declaration
variable inline2 : line; --line number declaration --test
file file_RESULTS : text;
variable inputdata : std_logic_vector(7 downto 0);
variable inputdata2 : std_logic_vector(7 downto 0); --test
begin
wait until rising_edge(clock);
while not endfile(infile) loop
readline(infile, inline);
inline := new string'(inline.all); --I was hoping this refresh the inline
while (SeqCount < 5) loop
inline := new string'(inline.all); --to copy line data to a new line
while inline.all'length /= 0 loop
hread (inline, inputdata);
readdatainput <= inputdata;
for i in inputdata'range loop
Bitreading <= inputdata(i);
IN_SRX2_BPSKDAT1 <= inputdata(i);
wait until rising_edge(clock);
end loop;--end of byte
inline := new string' (inline2.all);
end loop;-- end of line
SeqCount <= SeqCount+1; --this loops the program to read it a few more times.
end loop; -- end of while loop condition go to next line.
Seqcount <= 1;
end loop; -- end of file, it is suppose to repeat here
file_close(infile);
end process reading;
endoffile <='1'; --set signal to tell end of file read file is reached.
END ARCHITECTURE arch_name;
It is able to read the first line of data and repeat for the number of times of loop however it doesnt go on to the next line.
I need to get the length of a text file in Vivado during simulation. I tried below piece of code but I got an error.
file my_input : TEXT open READ_MODE is "/home/sukru/MD5.dat";
variable my_line : LINE;
variable input_line : LINE;
variable length : integer;
readline(my_input, input_line);
read(input_line, length);
writeline(output, input_line); -- optional, write to std out
write(input_line, integer'(length));
writeline(output, input_line);
The error message is this.
Error: TEXTIO function READ: read a non-integer, an integer is expected
a
-2147483648
I can read text's index but the length is non-sense value. Someone direct me how can I get the length of any text file.
VHDL at present has no way of interfacing to the host operating system to determine a file length.
There's an equivalency between bytes and the VHDL type character (see IEEE Std 1076-2008).
Normative references
...
ISO/IEC 8859-1:1998, Information technology—8-bit single-byte coded graphic character sets—Part 1: Latin alphabet No. 1.
Also see 16.3 Package standard, type character where all 256 enumeration values for a single-byte character are included.
That means we can count characters in a file:
use std.textio.all;
entity length_in_bytes is
end entity;
architecture foo of length_in_bytes is
impure function file_length (file_name: string) return integer is
type char_file is file of character;
file file_in: char_file open read_mode is file_name;
variable char_buffer: character;
variable length: integer := 0;
begin
while not ENDFILE(file_in) loop
read(file_in, char_buffer);
length := length + 1;
end loop;
file_close(file_in);
-- report file_name & " length = " & integer'image(length);
return length;
end function;
signal filelength: natural;
begin
filelength <= file_length("md5.dat");
process
begin
wait for 0 ns; -- skip default signal value;
report "file md5.dat length = " & integer'image(filelength);
wait;
end process;
end architecture;
The length returned by the function call will match the length the host operating system provides.
The file_close leaves the file unlocked for further use and reads of an open file are sequential from file open.
This line reads a line from the file:
readline(my_input, input_line);
This line tries to read an integer (destructively) from the line:
read(input_line, length);
It doesn't return the length of the file (or the line). You don't supply the file you are trying to read (it would have been better had you done so - see this ), but my guess is that it doesn't contain an integer and hence your error message.
If you want to get the length of any text file, you need to read every line in the file, find each's length and add them. It is easy to find the length of each line, because type line does have a 'length attribute, so the length of each line will be:
input_line'length
(Though note that the 'length attribute does not include the end-of-line character.) By the way, this line won't display what you've just read, because the read (if successful) is destructive:
writeline(output, input_line); -- optional, write to std out
(A "destructive read" is a read which removes the data as well as reading it.)
I have a problem in synthesis with my VHDL code : I am trying to get the logarithm value of an input signal S_ink:
My code :
entity ....
....
architecture rtl of myEntity is
attribute syn_looplimit : integer;
attribute syn_looplimit of loopabc : label is 16384;
logcalc:process(I_clk)
variable temp : integer;
variable log : integer;
begin
if(I_clk'event and I_clk='1') then
if (IN_rst='0') then
S_klog<=0;
temp:=0;
log:=0;
else
temp := S_ink+1; --S_ink is an input of my entity (integer)
log:=0;
loopabc:while (temp/=0) loop
temp:=temp/2;
log :=log+1;
end loop loopabc;
S_klog<=3*log;
end if;
end if;
end process;
It works very well in simulation but doesn't synthesize.
The error message is : "While loop is not terminating. You can set the maximum of loop iterations with the syn_looplimit attribute"
However, this code synthesize (but that is not what I want)
entity ....
....
architecture rtl of myEntity is
attribute syn_looplimit : integer;
attribute syn_looplimit of loopabc : label is 16384;
logcalc:process(I_clk)
variable temp : integer;
variable log : integer;
begin
if(I_clk'event and I_clk='1') then
if (IN_rst='0') then
S_klog<=0;
temp:=0;
log:=0;
else
temp := 3000; -- a random constant value
log:=0;
loopabc:while (temp/=0) loop
temp:=temp/2;
log :=log+1;
end loop loopabc;
S_klog<=3*log;
end if;
end if;
end process;
When the synthesis tool translates the design, it will make a circuit with a topology that does not depend on the data values, but where the wires carries the data values. The circuit must have a fixed calculation latency between each level of flip-flops, so timing analysis can determine if the amount of logic between flip-flops can fit for the specified frequency. In this process any loops are unrolled, and you can think of this as converting the loop to a long sequence of ordinary (non-loop) statements. To do this unrolling, the synthesis tool must be able to determine the number of iterations in the loops, so it can repeated the loop body this number of times when doing loop unrolling.
In the first code example the number of iterations in the loop depends on the S_ink value, so the synthesis tool can't unroll the loop to a fixed circuit, since the circuit depends on the data value.
In the second code example the synthesis tool can determine the number of iterations in the loop, thus do the unrolling to a fixed circuit.
One way to address this is make the algorithm with a fixed number of iteration, where this number of iterations can handle the worst case input data, and where any superfluous iteration on other input data will not change the result.
Solution :
process(I_clk)
variable temp : integer;
variable log : integer;
begin
if(I_clk'event and I_clk='1') then
if (IN_rst='0') then
S_klog<=0;
temp:=0;
log:=0;
else
temp := S_ink+1;
log:=0;
for I in 1 to 14 loop
temp := temp/2;
if (temp /=0) then
log :=log+1;
end if;
end loop;
S_klog<=3*log; -- 3*log because of my application
end if;
end if;
end process;