Reading text length in Vivado - vhdl

I need to get the length of a text file in Vivado during simulation. I tried below piece of code but I got an error.
file my_input : TEXT open READ_MODE is "/home/sukru/MD5.dat";
variable my_line : LINE;
variable input_line : LINE;
variable length : integer;
readline(my_input, input_line);
read(input_line, length);
writeline(output, input_line); -- optional, write to std out
write(input_line, integer'(length));
writeline(output, input_line);
The error message is this.
Error: TEXTIO function READ: read a non-integer, an integer is expected
a
-2147483648
I can read text's index but the length is non-sense value. Someone direct me how can I get the length of any text file.

VHDL at present has no way of interfacing to the host operating system to determine a file length.
There's an equivalency between bytes and the VHDL type character (see IEEE Std 1076-2008).
Normative references
...
ISO/IEC 8859-1:1998, Information technology—8-bit single-byte coded graphic character sets—Part 1: Latin alphabet No. 1.
Also see 16.3 Package standard, type character where all 256 enumeration values for a single-byte character are included.
That means we can count characters in a file:
use std.textio.all;
entity length_in_bytes is
end entity;
architecture foo of length_in_bytes is
impure function file_length (file_name: string) return integer is
type char_file is file of character;
file file_in: char_file open read_mode is file_name;
variable char_buffer: character;
variable length: integer := 0;
begin
while not ENDFILE(file_in) loop
read(file_in, char_buffer);
length := length + 1;
end loop;
file_close(file_in);
-- report file_name & " length = " & integer'image(length);
return length;
end function;
signal filelength: natural;
begin
filelength <= file_length("md5.dat");
process
begin
wait for 0 ns; -- skip default signal value;
report "file md5.dat length = " & integer'image(filelength);
wait;
end process;
end architecture;
The length returned by the function call will match the length the host operating system provides.
The file_close leaves the file unlocked for further use and reads of an open file are sequential from file open.

This line reads a line from the file:
readline(my_input, input_line);
This line tries to read an integer (destructively) from the line:
read(input_line, length);
It doesn't return the length of the file (or the line). You don't supply the file you are trying to read (it would have been better had you done so - see this ), but my guess is that it doesn't contain an integer and hence your error message.
If you want to get the length of any text file, you need to read every line in the file, find each's length and add them. It is easy to find the length of each line, because type line does have a 'length attribute, so the length of each line will be:
input_line'length
(Though note that the 'length attribute does not include the end-of-line character.) By the way, this line won't display what you've just read, because the read (if successful) is destructive:
writeline(output, input_line); -- optional, write to std out
(A "destructive read" is a read which removes the data as well as reading it.)

Related

How to write new line to file in VHDL?

I would like to separate my data with new line character in an output file, but the following codes result in error "can't resolve overload for procedure call":
write(out_line, "\n");
write(out_line, "");
write(out_line, '');
An example code how I want to use it:
ENTITY writer IS
PORT ( clk : IN STD_LOGIC := '0'; start : IN STD_LOGIC := '0');
END ENTITY;
ARCHITECTURE arch OF writer IS
SIGNAL vect : STD_LOGIC_VECTOR (2 downto 0) := "000";
TYPE state_type IS (init, write_file);
SIGNAL state : state_type := init;
BEGIN
PROCESS (clk, start)
FILE out_file : text;
VARIABLE out_line : line;
BEGIN
IF rising_edge(clk) THEN
CASE state IS
WHEN init =>
IF start = '1' THEN
state <= write_file;
ELSE
state <= init;
END IF;
WHEN write_file =>
state => init;
FOR i IN 0 TO 10 LOOP
write(out_line, vect);
writeline(out_file, out_line);
-- write(out_line, "\n"); <--
-- write(out_line, ""); <--
-- write(out_line, ''); <-- None of these work
writeline(out_file, out_line);
END LOOP;
END CASE;
END IF;
END PROCESS;
END ARCHITECTURE;
So I would like to know, is it possible in VHDL? If yes, how?
The following will consistently give you a single blank line:
write(out_line, string'(""));
writeline(out_file, out_line);
I suspect what #Dani posted may be tool dependent. For example while on one popular simulator, the following produces one line feed:
write(out_line, LF);
writeline(out_file, out_line);
However when I add a space after the LF, I get two lines:
write(out_line, LF & ' ');
writeline(out_file, out_line);
Creating a minimal, complete and verifiable example from the question's incomplete sample code:
library ieee; -- ADDED
use ieee.std_logic_1164.all; -- ADDED
use std.textio.all; -- ADDED
-- use ieee.std_logic_textio.all; -- ADDED for revisions earlier than -2008
ENTITY writer IS
-- PORT ( clk : IN STD_LOGIC := '0'; start : IN STD_LOGIC := '0');
END ENTITY;
ARCHITECTURE arch OF writer IS
SIGNAL vect : STD_LOGIC_VECTOR (2 downto 0) := "000";
-- TYPE state_type IS (init, write_file);
-- SIGNAL state : state_type := init;
BEGIN
PROCESS -- (clk, start)
FILE out_file : text;
VARIABLE out_line : line;
BEGIN
file_open(out_file, "some_file", WRITE_MODE); -- ADDED
-- IF rising_edge(clk) THEN
-- CASE state IS
-- WHEN init =>
-- IF start = '1' THEN
-- state <= write_file;
-- ELSE
-- state <= init;
-- END IF;
-- WHEN write_file =>
-- state => init;
FOR i IN 0 TO 10 LOOP
write(out_line, vect);
writeline(out_file, out_line);
-- write(out_line, "\n"); <--
-- write(out_line, ""); <--
-- write(out_line, ''); <-- None of these work
writeline(out_file, out_line);
END LOOP;
-- END CASE;
-- END IF;
wait; -- ADDED
END PROCESS;
END ARCHITECTURE;
demonstrates a way to get a blank line in the output:
some_file contents:
000
000
000
000
000
000
000
000
000
000
000
The second writeline procedure call produces an empty line without an intervening write procedure call.
Why is seen in IEEE Std 1076-2008 16.4 Package TEXTIO:
Procedures READLINE, WRITELINE, and TEE declared in package TEXTIO read and write entire lines of a file of type TEXT. Procedure READLINE causes the next line to be read from the file and returns as the value of parameter L an access value that designates an object representing that line. If parameter L contains a non-null access value at the start of the call, the procedure may deallocate the object designated by that value. The representation of the line does not contain the representation of the end of the line. It is an error if the file specified in a call to READLINE is not open or, if open, the file has an access mode other than read-only (see 5.5.2). Procedures WRITELINE and TEE each cause the current line designated by parameter L to be written to the file and returns with the value of parameter L designating a null string. Procedure TEE additionally causes the current line to be written to the file OUTPUT. If parameter L contains a null access value at the start of the call, then a null string is written to the file or files. If parameter L contains a non-null access value at the start of the call, the procedures may deallocate the object designated by that value. It is an error if the file specified in a call to WRITELINE or TEE is not open or, if open, the file has an access mode other than write-only.
The language does not define the representation of the end of a line. An implementation shall allow all possible values of types CHARACTER and STRING to be written to a file. However, as an implementation is permitted to use certain values of types CHARACTER and STRING as line delimiters, it might not be possible to read these values from a TEXT file.
A line feed (LF) format effector occurring as an element of a string written to a file of type TEXT, either using procedure WRITELINE or TEE, or using the WRITE operation implicitly defined for the type TEXT, is interpreted by the implementation as signifying the end of a line. The implementation shall transform the LF into the implementation-defined representation of the end of a line.
...
For each WRITE, OWRITE, and HWRITE procedure, after data is appended to the string value designated by the parameter L, L designates the entire line. The procedure may modify the value of the object designated by the parameter L at the start of the call or may deallocate the object.
If deallocation occurs out_line will have a value of null after a writeline call and a null string is written in the immediately following writeline call which also provides an end of line.
If the object value accessed by out_line is a null array (having no elements, 5.3.2.2 Index constraints and discrete ranges, a null string) the immediately following writeline call will result in an end of line being written to the file.
In essence your code example already contains one of these methods for writing a blank line, which depends on whether deallocation is used conditionally (may).
Variants of allocate() and free() can be relatively expensive in terms of execution time and when the size of the allocated object and it's element size is known a smaller 'allocated' object can be written to the same object space saving simulation time. The simulation kernel representation of an array object can have bounds separate from the array value, deallocation and re-allocation can be reserved for when the object size is larger than the previously allocated size or an explicit deallocate call occurs.
There's also a requirement that an implementation translate an LF character to an end of line in a write to a file. This is the other mechanism that allows you to write an LF character as the last or only character to a line and get a following blank line.
You could also explicitly write a null string to out_line
write(out_line, string'(""));
prior to the second writeline call. The qualified expression provides the type of the string literal unlike the attempt commented out in the original question where the type of the string literal can't be determined. See 9.3.2 Literals "... The type of a string or bit string literal shall be determinable solely from the context in which the literal appears, excluding the literal itself but using the fact that the type of the literal shall be a one-dimensional array of a character type. ...". The procedure write would be ambiguous in this context, failing overload resolution (12.5 The context of overload resolution).
Finally after a lot of searching and trying I found that the following code works:
write(out_line, lf);
writeline(out_file, out_line);
I found that write(out_line, cr); does the same thing, and write(out_line, nul); adds ' ' character between the outputs.

Unable to open file in 'r' mode

I'm trying to read from a text file in my synthesis code. However, I get an error when I try to open a file that does exist.
I have tried placing the text file in various folders because I figured the problem was that the program is unable to find the text file. None of these different positions have worked.
type chunk is array (INPUTNUM downto 0) of std_logic_vector (WIDTH-1 downto 0);
impure function ReadfromFile (FileName: in string) return chunk is
FILE IN_FILE : text open read_mode is FileName;
variable BUFF : line;
variable val : chunk;
begin
for i in 0 to INPUTNUM loop
readline (IN_FILE, BUFF);
read (BUFF, val(i));
end loop;
return val;
end function;
signal w : chunk := ReadfromFile("neuron_text.txt");
I expected the file to be read and the values to be stored in the w signal. However, when I run the RTL analysis I get the error : "[Synth 8-3302] unable to open file 'neuron_text.txt' in 'r' mode" as well as "[Synth 8-421] mismatched array sizes in rhs and lhs of assignment". I assume the second error is a result of the first one though.
Vivado runs four, five or six levels of hierarchy lower down than you think (depending on the version you're running). Try:
signal w : chunk := ReadfromFile("../../../../neuron_text.txt");
or
signal w : chunk := ReadfromFile("../../../../../neuron_text.txt");
or even
signal w : chunk := ReadfromFile("../../../../../../neuron_text.txt");
If this still doesn't work, try opening a file for writing, seeing where it gets creating and using that information to your advantage.

Copying ISim results as strings/text

I'm creating a VHDL project, and using ISim to simulate beforehand - which is all fine.
However, my results use fixed point - and although Isim can represent its signals as a range of radix's, unsurprisingly, fixed point decimal isn't one of them.
Hence I'd like to get the current value of each signal as text but the "copy" function only copies the entity and signal name, and not the string value.
For example
I want to get the value of "[00010000, 00020000...etc etc] but I actually just get the value of "/fixedpointtb/UUT/s1_fcs[0]" i.e. entity name.
Common sense says there must be a simple way of doing this but I can't see how!
You can use VHDL's file I/O capabilities in your testbench (at top-level) to convert the signals from DUT into a human readable string and write it to STDOUT or into a file.
A coarse overview on file I/O.
VHDL has several packages and procedures/functions for file I/O and string operations.
std.textio
VHDL defines an access type (a pointer) called line for string and a basic file type text for text files.
Usage:
use std.textio.all;
Declarations from std.textio:
-- types
type line is access string;
type text is file of string;
-- STD files
file input : text open read_mode is "STD_INPUT";
file output : text open write_mode is "STD_OUTPUT";
-- procedures (some with overloads)
read (<lineVar>, <vhdlObji [,<status>]);
readline (<fileObj>, <lineVari);
write (<lineVar>, <vhdlObj> [,right|left, <width>]);
write (<lineVar>, <realObj> [,right|left, <width>, <digits>]);
write (<lineVar>, <timeObj> [,right|left, <width>, <unit>]);
writeline (<fileObj>, <lineVar>);
-- functions
endfile (<fileObj>) : boolean
ieee.std_logic_textio
This package declares more procedures to format std_logic values.
Usage:
library ieee;
use std.textio.all;
use ieee.std_logic_1164.all;
use ieee.std_logic_textio.all;
Declarations from ieee.std_logic_textio:
read (<lineVar>, <vhdlObj> [,<status>]); -- binary
hread (<lineVar>, <vhdlObj> [,<status>]); -- hexadecimal
oread (<lineVar>, <vhdlObj> [,<status>]); -- octal
write (<lineVar>, <vhdlObj> [,right|left, <width>]); -- binary
hwrite (<lineVar>, <vhdlObj> [,right|left, <width>]); -- hexadecimal
owrite (<lineVar>, <vhdlObj> [,right|left, <width>]); -- octal
Source: VHDL Kompakt (German VHDL book from Universität Hamburg)
Usage example
The following example writes the value of mySignal to a logfile and reports the time.
signal mySignal : STD_LOGIC_VECTOR(7 downto 0);
-- ....
process
file LogFile : TEXT open WRITE_MODE is "logfile.log";
variable LineBuffer : LINE;
begin
write(LineBuffer, ( STRING'("========================================")));
write(LineBuffer, (CR & STRING'("TESTBENCH REPORT")));
write(LineBuffer, (CR & STRING'("========================================")));
writeline(LogFile, LineBuffer);
wait until mySignal /= x"00";
wait until rising_edge(Clock);
for i in 0 to 7 loop
wait until rising_edge(Clock);
write(LineBuffer, "Time " & to_string(now, 1) & " Value 0x" & raw_format_slv_hex(mySignal));
writeline(LogFile, LineBuffer);
end loop;
end process;
now is a built-in function, representing the current simulation time. It is formatted by to_string, which expects a time and a precision. The signal mySignal is formatted by raw_format_slv_hex. This function formats a STD_LOGIC_VECTOR of arbitrary size to a hexadecimal string.
The file should have such content:
========================================
TESTBENCH REPORT
========================================
Time 50 ns Value 0x08
Time 60 ns Value 0x09
Time 70 ns Value 0x0A
Time 80 ns Value 0x0B
Time 90 ns Value 0x0C
....
One last hint
write procedures append there data to the LineBuffer string. When you call writeline, the buffer is written to the file and the LineBuffer is empty after that operation.
And finally, here is an example snippet on how to read a RAM/ROM initialization file and convert it into a generic memory representation.

How to subtract two hexadecimal numbers in VHDL?

I am reading two hex numbers from a text file and I want to be able to subtract the two numbers and place the result into another variable how would I go about doing this? Is it possible to make a function to do this that I can then place in a package file and reference so that my code is more readable and less cluttered?
many thanks,
For conversion of line to unsigned, VHDL-2008 provides a hread procedure in then numeric_bit package. A function that takes string and returns natural could look like:
library ieee;
use ieee.numeric_bit.all;
library std;
use std.textio.all;
...
function hex_to_nat(s : string) return natural is
variable line_v : line;
variable value_v : unsigned(4 * s'length - 1 downto 0); -- Bits to match value in hex
begin
line_v := new string'(s);
hread(line_v, value_v); -- Assertion in case of conversion error
deallocate(line_v); -- Avoid memory leak
return to_integer(value_v); -- Assertion in case of conversion error
end function;
If the text read from the file is already of line type, then just use the hread procedure directly.

Is it possible to check the length of an input text file?

In my VHDL project, my input is going to be extracted from a text file containing n bits of 1's and 0's. I am trying to make it as general as possible. I am familiar with how to read and write on a text file using test-bench, but I don't know how to check its length.
My code normally takes 64 bit as input, pass them through all the blocks and generate an output. If the remaining bits length is less than 64 then it passes through a specific block.
Let's say the text file contains 1000 bits. 15 x 64 = 960. 960 bits will pass through all blocks, the remaining 40 will pass by a specific block. This looks straight forward but in order for me to do such operations i need to know the length of the text file. If anyone can help that would be very beneficial.
The VHDL data structure length should be considered, not the file length since that is implementation specific and not VHDL specified.
If the bits are in one long string that is to be chopped up into 64-bit pieces with a remainder, then the entire string can be read into a VHDL line type, and reading from that line to a std_logic_vector type can then depend on the remaining bits (characters) in the line.
Below is a code example doing so:
library ieee;
use std.textio.all;
use ieee.std_logic_textio.all; -- Synopsys package; required for VHDL-2002 only
architecture syn of tb is
begin
process is
variable myl_v : line;
file txt_file : text;
variable slv_v : std_logic_vector(63 downto 0);
begin
file_open(txt_file, "input.txt", read_mode);
readline(txt_file, myl_v);
while myl_v'length > 0 loop
if myl_v'length >= slv_v'length then -- Full slv_v
report "Full...: " & myl_v.all(1 to slv_v'length);
read(myl_v, slv_v);
else -- Reduced slv_v
report "Reduced: " & myl_v.all(1 to myl_v'length);
read(myl_v, slv_v(myl_v'length - 1 downto 0)); -- Place reduced at LSBs
end if;
end loop;
file_close(txt_file);
wait;
end process;
end architecture;
Btw, to answer the question of "length of an input text file", then the length in characters can be determined by reading as many characters from the file as possible, for example with code like:
impure function file_length_in_characters(filename : string) return natural is
type char_file_t is file of character;
file char_file : char_file_t;
variable char_v : character;
variable res_v : natural;
begin
res_v := 0;
file_open(char_file, filename, read_mode);
while not endfile(char_file) loop
read(char_file, char_v);
res_v := res_v + 1;
end loop;
file_close(char_file);
return res_v;
end function;

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