#
# Makefile
#
# compiler to use
CXX = clang++
# flags to pass compiler
CXXFLAGS = -ggdb3 -O0 -std=c++11 -Wall -Werror -pedantic-errors
# flags for the C PreProcessor
CPPFLAGS = -MMD
# The maintainer's variant of CXXFLAGS
AM_CXXFLAGS =
# The command used to actually compile a C++ source file.
# The file name is appended to form the complete command line.
CXXCOMPILE =
# The command used to actually link a C++ program
CXXLINK =
# space-separated list of header files
HDRS =
# space-separated list of libraries, if any,
# each of which should be prefixed with -l
LIBS = -lm -lpthread
# default target
# require that an argument be provided at the command line
# for the target name
TARGET = $(target)
> problem with this line
> It is just targeting the single .cpp
> But when I want make project folder
#
# Makefile
#
# compiler to use
CXX = clang++
# flags to pass compiler
CXXFLAGS = -ggdb3 -O0 -std=c++11 -Wall -Werror -pedantic-errors
# flags for the C PreProcessor
CPPFLAGS = -MMD
# The maintainer's variant of CXXFLAGS
AM_CXXFLAGS =
# The command used to actually compile a C++ source file.
# The file name is appended to form the complete command line.
CXXCOMPILE =
# The command used to actually link a C++ program
CXXLINK =
# space-separated list of header files
HDRS =
# space-separated list of libraries, if any,
# each of which should be prefixed with -l
LIBS = -lm -lpthread
# default target
# require that an argument be provided at the command line
# for the target name
TARGET = $(target)
I cannot able to target header file and corresponding .cpp dependencies
all: $(TARGET)
$(TARGET): $(TARGET).cpp ; $(CXX) $(CXXFLAGS) $(CPPFLAGS) $(AM_CXXFLAGS) $(CXXCOMPILE) $(CXXLINK) $(HDRS) -o $(TARGET) $(TARGET).cpp $(LIBS)
# housekeeping
clean:
rm -f core
Related
I'm trying to compile a large C++ project with source files in several subdirectories of src.
My Makefile looks like this:
# ---------- Compiler and linker directives ----------
CXX = g++-11
CXXFLAGS = -std=c++17 -fopenmp -MD -g -Wall -pedantic
# LDFLAGS = -Wl,--gc-sections
# Output directory after linking
BIN_PATH = ../bin
BUILD_PATH = ../build
# ------- System Include --------------
# Change ~/include as necessary for your architecture
INC_FLAGS = -I../include -I/opt/homebrew/include
# -------- Establishing objects and sources ------
RATE_SRC = $(wildcard hartreefock/*.cpp) $(wildcard struct_hartreefock/*.cpp) $(wildcard numerical/*.cpp)
RATE_OBJ = $(addprefix $(BUILD_PATH)/,$(RATE_SRC:.cpp=.o)))
# ------------- Specific Include -----------
# RATE_HEADERS = $(wildcard hartreefock/*.hpp) $(wildcard struct_hartreefock/*.hpp) $(wildcard numerical/*.hpp)
RATE_DIR = hartreefock struct_hartreefock numerical
RATE_INC = $(addprefix -I,$(RATE_DIR))
# ---------- Libraries needed for linking ----------
# Change or remove ~/lib as necessary for your architecture
LIB_PATH = -L/opt/homebrew/lib
# Generic .cc -> .o rule
$(BUILD_PATH)/%.o: %.cpp
#mkdir -p $(#D)
$(CXX) $(CXXFLAGS) $(INC_FLAGS) $(RATE_INC) $< -c -o $#
# ---------- Linking rules ----------
# Generic .o -> exec rule: uses all prerequisites (meant to be .o files)
ratecalc: $(RATE_OBJ)
$(CXX) $(CXXFLAGS) $(INC_PATH) $(A_RATE_INC) $(LDFLAGS) $^ \
$(LIB_PATH) -o $(BIN_PATH)/$#
# TODO
# simulate:
echo:
echo "$(RATE_OBJ)"
echo "$(BUILD_PATH)"
# Cleanup:
.PHONY: clean build_directories
clean:
-rm -r $(BUILD_PATH)/**
Bizarrely, this seems to do the right thing until I get to one specific file:
make clean
make ratecalc
g++-11 -std=c++17 -fopenmp -MD -g -Wall -pedantic -I../include -I/opt/homebrew/include -Ihartreefock -Istruct_hartreefock -Inumerical struct_hartreefock/RateData.cpp -c -o ../build/struct_hartreefock/RateData.o
g++-11 -std=c++17 -fopenmp -MD -g -Wall -pedantic -I../include -I/opt/homebrew/include -Ihartreefock -Istruct_hartreefock -Inumerical numerical/Constant.cpp -c -o ../build/numerical/Constant.o
make: *** No rule to make target `../build/numerical/wignerSymbols.o)', needed by `ratecalc'. Stop.
This is especially strange because Constant.cpp and wignerSymbols.cpp are in the same directory. Manually running with this target compiles the object file as needed,
make ../build/numerical/wignerSymbols.o
g++-11 -std=c++17 -fopenmp -MD -g -Wall -pedantic -I../include -I/opt/homebrew/include -Ihartreefock -Istruct_hartreefock -Inumerical numerical/wignerSymbols.cpp -c -o ../build/numerical/wignerSymbols.o
but this is not recognised as satisfying the dependency for the ratecalc rule.
It might be significant that wignerSymbols.cpp is the very last entry in RATE_OBJ, but to be honest I can't understand what's happening here.
For completeness: I'm using GNU make 3.81 on an M1 macbook air.
Typo:
RATE_OBJ = $(addprefix $(BUILD_PATH)/,$(RATE_SRC:.cpp=.o)))
There is an extra close paren here, which you can see in your error message:
make: *** No rule to make target `../build/numerical/wignerSymbols.o)', ...
I'm using mingw32-make to run my makefile. The contents of the Makefile are the following:
#OBJS specifies which files to compile as part of the project
OBJS = SDLpp.o SDLpp_exception.o SDLpp_window.o
#CC specifies which compiler we're using
CC = g++
#INCLUDE_PATHS specifies the additional include paths we'll need
INCLUDE_PATHS = -IC:\mingw_dev_lib\include\SDL2 \
-IC:\mingw_dev_lib\include\SDL_image \
-IC:\mingw_dev_lib\include\SDLpp
#LIBRARY_PATHS specifies the additional library paths we'll need
LIBRARY_PATHS = -LC:\mingw_dev_lib\lib
#COMPILER_FLAGS specifies the additional compilation options we're using
# -w suppresses all warnings
# -Wall includes all warnings
# -Wl,-subsystem,windows gets rid of the console window
COMPILER_FLAGS = -Wall
#LINKER_FLAGS specifies the libraries we're linking against
LINKER_FLAGS = -lmingw32 -lSDL2main -lSDL2 -lSDL2_image
#LIB_NAME specifies the name of our library
LIB_NAME = libSDLcpp.a
#This is the target that compiles our executable
all : $(OBJS)
ar rvs $(LIB_NAME) $(OBJS)
%.o : %.c
$(CC) $< $(INCLUDE_PATHS) $(LIBRARY_PATHS) $(COMPILER_FLAGS) -c $(LINKER_FLAGS) -o $#
^(the white-space before the commands are tabs)^
When run, the shell outputs
g++ -c -o SDLpp.o SDLpp.cpp
which indicates that the other variables are not being expanding in the first pattern rule. Oddly, only CC is expanding into g++. Why is this happening?
The issue is not one of non-expanding variables. Rather, the makefile is using the default rule instead of the one you provided.
The reason may be that your rule uses *.c, while you likely have *.cpp files, IIRC.
I have a code that is about 8,000 lines and is contained in the same one big bigcode.f90 file. It compiles without problems from the command line with intel compiler with the options:
mpif90 bigcode.f90 -r8 -O2 -xHost -override-limits -o output.out
I want to split this large file into modules and link them using makefile. Below I am listing the makefile. (So here I have main.f90, and also 8 modules linked to it, such as modparams.o and other 7). So I just broke the bigcode.f90 into 9 files. The problem is that when I compile with the makefile, it complains about things like
subroutine ended with "end" statement instead of "end subroutine"
integer passed to reals
some name conflicts between variable names and subroutine names.
All these may well be bad style. However the original bigcode.f90 had all of these, and it did not prevent it from compiling at all. I want to first replicate the results between the bigcode.f90 and the split version - and then I will make other changes.
I also made a copy of this makefile without any OBJECTS to link (just the single bigcode.f90), and that also compiled without any complains. Could somebody help me understand why is there inconsistency about what the compiler complains when there is one file versus when there are several linked files?
# DEFAULT FLAGS
CFLAGS := -I$(CPATH) -I$(F90_MODULES_PATH)
F90 := mpif90
# ADD ALL LIBRARIES HERE (with -l$LIBRARY_NAME)
LDFLAGS := -llapack -v
# ADD ALL SOURCE FILES HERE (with .o extension)
OBJECTS := modparams.o
OBJECTS += modleeplex.o
OBJECTS += modutilsmain.o
OBJECTS += modecon.o
OBJECTS += modindirect.o
OBJECTS += modijutils.o
OBJECTS += modselectstata.o
OBJECTS += modfcn.o
# ADD ADDITIONAL COMPILER FLAGS HERE
CFLAGS += -fbounds-check
CFLAGS += -ffree-line-length-350
CFLAGS += -r8
CFLAGS += -O2
CFLAGS += -xHost
CFLAGS += -override-limits
# ADD ADDITIONAL MODULE FOLDERS HERE (with -I$PATH_TO_FOLDER)
F90_MODULES += -I.
all: main
main: main.f90 $(OBJECTS)
$(F90) $(CFLAGS) $(LDFLAGS) $(OBJECTS) $< -o $#
%.o : %.f90
$(F90) -c $< $(CFLAGS) $(F90_MODULES) $(LDFLAGS) -o $#
clean:
rm -rf $(OBJECTS) *.mod
When I compile, I get the following, and then a long list of errors.
mpif90 -c modfcn.f90 -I/opt/intel/composer_xe_2013.5.192/mkl/include:/opt/intel/composer_xe_2013.5.192/tbb/include:/opt/intel/composer_xe_20 13.5.192/mkl/include:/opt/intel/composer_xe_2013.5.192/tbb/include -I -fbounds-check -ffree-line-length-350 -r8 -O2 -xHost -override-lim its -I. -llapack -v -o modfcn.o
ifort: command line warning #10006: ignoring unknown option '-ffree-line-length-350'
ifort: command line remark #10010: option '-pthread' is deprecated and will be removed in a future release. See '-help deprecated'
ifort version 13.1.3
I am looking to write a makefile to automate the compiling of a project that I am working on where the files may, or may not, change in number. I also need to be able to quickly tell make to compile the files as a debug build or a release build (differentiated by a command line define). After some research, I came upon pattern rules and made one. Here is the code I have so far:
# Our folders
# ODIR - The .o file directory
# CDIR - The .cpp file directory
# HDIR - The .hpp file directory
ODIR = obj
CDIR = src
HDIR = inc
# Get our compiler and compiler commands out of the way
# CC - Our compiler
# CFNO - Our compiler flags for when we don't have an output file
# CF - Our compiler flags. This should be appended to any compile and should
# have the name of the output file at the end of it.
# OF - Object flags. This should be appended to any line that is generating
# a .o file.
CC = g++
CFNO = -std=c++11 -wall -Wno-write-strings -Wno-sign-compare -lpaho-mqtt3c -pthread -O2 -I$(HDIR)
CF = $(CFNO) -o
OF = -c
# Our project/output name
NAME = tls_test
# Set out Debug and Release settings, as well as any defines we will use to identify which mode we are in
# NOTE: '-D[NAME OF DEFINE]' is how you create a define through the compile commands
DEBUG = -DDEBUG -g
RELEASE = -DRELEASE
# Our two compile modes
# eval allows us to create variables mid-rule
debug:
$(eval DR = $(DEBUG))
release:
$(eval DR = $(RELEASE))
# Our compiling commands
all:
$(CC) $(CF) $(NAME) $(ODIR)/*.o
# NOTE: $# is the end product being created and $< is the first of the prerequisite
$(ODIR)/%.o: $(CDIR)/%.c
echo "$(CC) $(DR) $(OF) $(CF) $# $<"
The issue that I am having is with the order that I need things to run in. The command line call should tell make to use either debug or release, which sets a make variable, then call all. all should then run the pattern rule at the bottom before running the line currently in the all rule. So, how do I make a pattern rule a dependency and how do I call a rule from another rule?
Use target-specific variables
While not strictly necessary, separating your flags goes a long way in managing build options, you can then use target-specific variable appends to toggle the flags. While you're at it you might as well use the built-in variable names.
I've also added dependency generation (-MMD -MP) because it's always useful.
ODIR := obj
CDIR := src
HDIR := inc
SRCS := $(wildcard $(CDIR)/*.cpp)
OBJS := $(SRCS:$(CDIR)/%.cpp=$(ODIR)/%.o)
DEPS := $(OBJS:%.o=%.d)
CPPFLAGS := -I$(HDIR) -MMD -MP
CXXFLAGS := -std=c++11 -Wall -Wno-write-strings -Wno-sign-compare -pthread -O2
LDFLAGS := -pthread
LDLIBS := -lpaho-mqtt3c
NAME := tls_test
.PHONY: debug release clean
debug: CPPFLAGS+=-DDEBUG
debug: CXXFLAGS+=-g
release: CPPFLAGS+=-DRELEASE
debug release: $(NAME)
$(NAME): $(OBJS)
$(CXX) $(LDFLAGS) $^ $(LDLIBS) -o $#
$(OBJS): $(ODIR)/%.o: $(CDIR)/%.cpp
$(CXX) $(CXXFLAGS) $(CPPFLAGS) -c $(OUTPUT_OPTION) $<
clean: ; $(RM) $(NAME) $(OBJS) $(DEPS)
-include $(DEPS)
I`m having a makefile with Sub makes. I want to place the Output of the submakes in one Directory. Can anyone explain me how to do this right?
-root |
|-stub
|-test
|-source
|-out
|-makefile
all of my submakes shall place their *.o files in out. I`m getting Errors there is no File or Directory ./out/**.o if i add ../out to the Objectfile.
here is my submakefile
# makefile to generate UNIT-tests
# sub makefile for location stub
# define any directories containing header files other than /usr/include
# TODO
# define any libraries to link into executable:
# if I want to link in libraries (libx.so or libx.a) I use the -llibname
# option, something like (this will link in libmylib.so and libm.so:
LIBS =
# TODO define the C source files
SRCS = $(STUBS)
# define the C object files
#
# This uses Suffix Replacement within a macro:
# $(name:string1=string2)
# For each word in 'name' replace 'string1' with 'string2'
ODIR=../out
OBJ = $(SRCS:%.c=%.o)
# define the C compiler to use
CC = gcc
# define any compile-time flags
#compile without link
CFLAGS = -O0 -Wall -c -g -fmessage-length=0 -fprofile-arcs -ftest-coverage
#TODO Linkerflags
LFLAGS = --coverage
# define the executable file,
all: $(TARGET) $(OBJ)
$(CC) $(OBJ) $(CFLAGS) -o $(TARGET) $(LFLAGS) $(OBJ)
#echo +++ build of stub finished +++
clean:
$(RM) *.o *~ $(MAIN)
# DO NOT DELETE THIS LINE -- make depend needs it