I`m having a makefile with Sub makes. I want to place the Output of the submakes in one Directory. Can anyone explain me how to do this right?
-root |
|-stub
|-test
|-source
|-out
|-makefile
all of my submakes shall place their *.o files in out. I`m getting Errors there is no File or Directory ./out/**.o if i add ../out to the Objectfile.
here is my submakefile
# makefile to generate UNIT-tests
# sub makefile for location stub
# define any directories containing header files other than /usr/include
# TODO
# define any libraries to link into executable:
# if I want to link in libraries (libx.so or libx.a) I use the -llibname
# option, something like (this will link in libmylib.so and libm.so:
LIBS =
# TODO define the C source files
SRCS = $(STUBS)
# define the C object files
#
# This uses Suffix Replacement within a macro:
# $(name:string1=string2)
# For each word in 'name' replace 'string1' with 'string2'
ODIR=../out
OBJ = $(SRCS:%.c=%.o)
# define the C compiler to use
CC = gcc
# define any compile-time flags
#compile without link
CFLAGS = -O0 -Wall -c -g -fmessage-length=0 -fprofile-arcs -ftest-coverage
#TODO Linkerflags
LFLAGS = --coverage
# define the executable file,
all: $(TARGET) $(OBJ)
$(CC) $(OBJ) $(CFLAGS) -o $(TARGET) $(LFLAGS) $(OBJ)
#echo +++ build of stub finished +++
clean:
$(RM) *.o *~ $(MAIN)
# DO NOT DELETE THIS LINE -- make depend needs it
Related
I've been learning C++ for a few months now by just using an editor and my terminal to compile and run my programs. But I saw a need to be a bit more formal with my projects, so I'm trying to learn how to build a proper project file structure and also how to use Make.
Currently, I am using GNU Make 4.1. But I am having trouble to creating object files with Make, receiving the error:
make: *** No rule to make target 'build/%.o', needed by 'main'. Stop.
I've been looking all over for a solution, but none have worked so far.
Here is my makefile:
# Specify compiler
CC=gcc
# Specify linker
LINK=gcc
# Specify flags
CPPFLAGS = -Wall -g
# Specify directories
SRCDIR = ./src
OBJDIR = ./build
# Compile object files
$(OBJDIR)/%.o : $(SRCDIR)/%.cpp
$(CC) -c -o $# $< $(CPPFLAGS)
# Compile object files into binary
main : $(OBJDIR)/%.o
$(CC) -o $# $^
Consider the final rule...
# Compile object files into binary
main : $(OBJDIR)/%.o
$(CC) -o $# $^
Unfortunately $(OBJDIR)/%.o isn't expanded in the way in which you require. Assuming all of your source files are in $(SRCDIR) you can create a variable containing their names...
SRCFILES := $(wildcard $(SRCDIR)/*.cpp)
Now create a variable containing the corresponding object file paths...
OBJFILES := $(patsubst $(SRCDIR)/%.cpp,$(OBJDIR)/%.o,$(SRCFILES))
Now $(OBJFILES) should contain the list of object file paths on which main is dependent. So the final rule becomes...
main: $(OBJFILES)
$(CC) -o $# $^
Makefile specified in this question, compiling all the cpp programs in a folder but not with python embedded cpp programs.
all: myUB
sourcesC := $(wildcard ../src/*.cpp)
objectsC := $(patsubst %.cpp,%.o,$(sourcesC))
INPATH=-I"C:/Python27/include"
LIBPATH=-L"C:/Python27/libs"-lpython27
myUB:
#echo 'Building target $#'
g++ -O0 -Wall -c -g3 -fmessage-length=0 \
$(sourcesC)
del *.o
clean:
Your final makefile could look somthing like:
all: myUB
sourcesC := $(wildcard ../src/*.cpp)
# Not used
#objectsC := $(patsubst %.cpp,%.o,$(sourcesC))
INC = -IC:\Python27\include
LIBS = -LC:\Python27\libs -lpython27
myUB:
#echo 'Building target $#'
g++ -O0 -Wall -g3 -fmessage-length=0 -o myprog.out $(sourcesC) $(INC) $(LIBS)
clean:
rm myprog.out
update
For the undefined ref to WinMain(), it means the linker can't find this function in your code. Either you need to include a library/object that contains it or you can define it yourself in a cpp file like:
#include <windows.h>
int WINAPI (*MyDummyReferenceToWinMain)(HINSTANCE hInstance, ..., int
nShowCmd ) = &WinMain;
I got the function template from here.
But this seems to mean that you are creating a windows application instead of a console app which uses int main(...) entry point.
Update2
I have made a new makefile to do what you have asked for in your latest comment which seems to be to create one executable per source file - I am assuming each source file has its own main.
# Build vars
CXX = g++
CXX_FLAGS = -O0 -Wall -g3
INC = -IC:\Python27\includ
LIBS = -LC:\Python27\libs -lpython27
# Sources
SRC_DIR=src
SOURCES = $(wildcard $(SRC_DIR)/*.cpp)
$(info SOURCES: $(SOURCES))
# Executables
EXE_DIR=bin
EXECUTABLES = $(subst $(SRC_DIR)/,$(EXE_DIR)/,$(subst cpp,out,$(SOURCES)))
$(info EXECUTABLES: $(EXECUTABLES))
$(info ----)
# Directories
DIRS = $(EXE_DIR)
# Rule to create folders and compile executables
all: $(DIRS) $(EXECUTABLES)
# Pattern rule to build each executable
$(EXE_DIR)/%.out : $(SRC_DIR)/%.cpp
#echo "compiling $< --> $#"
#$(CXX) $(CXX_FLAGS) -o $# $< $(INC) $(LIBS)
# Rule to create output dirs
$(DIRS):
#echo "Creating output folders"
#mkdir -p $(EXE_DIR)
# Rule to clean up
clean:
#echo "Cleaning"
#rm -rf $(EXE_DIR)
This should create one executable in the folder bin/ for each source file (.cpp) in folder src/.
I'm modifying makefile of a code. After compiling, I see that some *.mod files are generated. looking online, I figured out they are module files, but I don't see a compilation rule for them. I'm trying to change the directory in which these files are generated. I can change the rule for object files, but I can't find the rule that generates *.mod files.
Looking at the makefile, can someone advise me if a line in this file generates them or how to change their directory. Here is the makefile:
# GNU Makefile
# Paths
SDIR=./solver
ODIR=./obj
_CASE=./WorkCases/problem
CASE=$(SDIR)/$(_CASE)
TOP = .
FC = ifort
FFLAGS = -fpp -O1 -DPTR_INTEGER8 -warn nousage
# Define rule to make .f90
$(ODIR)/%.o : $(SDIR)/%.f90
$(FC) -c $(FFLAGS) $< -o $#
# set executable name
EXEC = $(dir ${CASE})/$(basename $(notdir ${CASE})).out
# shared global variables
_SHARED_OBJ = shared_modules.o main_vars.o debug_vars.o
SHARED_OBJ = $(patsubst %,$(ODIR)/%,$(_SHARED_OBJ))
OBJ = ${_SHARED_OBJ} $(_CASE).PARAMS.o
OBJ = $(patsubst %,$(SDIR)/%,$(_OBJ))
MAIN_OBJ = $(ODIR)/main.o
main : ${SHARED_OBJ} $(OBJ) $(MAIN_OBJ)
$(FC) ${FFLAGS} $(OBJ) $(MAIN_OBJ) -o $(EXEC) -lstdc++ -shared-intel
You can specify the destination directory for the .mod files by using the -module compiler option.
-module <directory>
See the ifort documentation here:
You can use the module path compiler option to specify the directory
in which to create the module files. If you do not use this option,
module files are created in the current directory.
I am trying to create a Makefile and I am a bit stuck.
So far I have been compiling my 3 files (2 headers and one main program) as such:
gcc -c phypages.c -o phypages.o
gcc -c pagetable.c -o pagetable.o
gcc -c analysis.c -o analysis.o
gcc analysis.o phypages.o pagetable.o -o analysis
I would like to make a Makefile to help me out with this. When I compile and link the files without a Makefile everything works fine, however when I try to make a Makefile I get a bunch of errors. Could you give me some tips on how to go about making a basic Makefile?
This is a good start:
# Binary name
NAME = analysis
# Compiler settings
CC = gcc
CFLAGS += -Wall -Wextra
CFLAGS += -Werror
# Source files
SRCS = phypages.c \
pagetable.c \
analysis.c
# Object files
OBJS = $(SRCS:.c=.o)
RM = rm -f
# Default rule, it should call all your rules that create
# an executable, or build a library...
# Here, it calls only the $(NAME) rule, that builds `analysis`
all: $(NAME)
# Rule to build your object files and link them into a binary
$(NAME): $(OBJS)
$(CC) -o $(NAME) $(OBJS)
# Rule to remove object files
clean:
$(RM) $(OBJS)
# Rule to remove binary, calls the 'clean' rule first
fclean: clean
$(RM) $(NAME)
# Rule to remove object files and binary, then re-build everything
re: fclean all
# Rules that are not linked with a filename should be listed here
.PHONY: all clean fclean re
You can then run make analysis or simply make to build your program.
Next time you change a file, run make again and only the file you changed will be re-compiled, instead of the whole project.
I am looking to write a makefile to automate the compiling of a project that I am working on where the files may, or may not, change in number. I also need to be able to quickly tell make to compile the files as a debug build or a release build (differentiated by a command line define). After some research, I came upon pattern rules and made one. Here is the code I have so far:
# Our folders
# ODIR - The .o file directory
# CDIR - The .cpp file directory
# HDIR - The .hpp file directory
ODIR = obj
CDIR = src
HDIR = inc
# Get our compiler and compiler commands out of the way
# CC - Our compiler
# CFNO - Our compiler flags for when we don't have an output file
# CF - Our compiler flags. This should be appended to any compile and should
# have the name of the output file at the end of it.
# OF - Object flags. This should be appended to any line that is generating
# a .o file.
CC = g++
CFNO = -std=c++11 -wall -Wno-write-strings -Wno-sign-compare -lpaho-mqtt3c -pthread -O2 -I$(HDIR)
CF = $(CFNO) -o
OF = -c
# Our project/output name
NAME = tls_test
# Set out Debug and Release settings, as well as any defines we will use to identify which mode we are in
# NOTE: '-D[NAME OF DEFINE]' is how you create a define through the compile commands
DEBUG = -DDEBUG -g
RELEASE = -DRELEASE
# Our two compile modes
# eval allows us to create variables mid-rule
debug:
$(eval DR = $(DEBUG))
release:
$(eval DR = $(RELEASE))
# Our compiling commands
all:
$(CC) $(CF) $(NAME) $(ODIR)/*.o
# NOTE: $# is the end product being created and $< is the first of the prerequisite
$(ODIR)/%.o: $(CDIR)/%.c
echo "$(CC) $(DR) $(OF) $(CF) $# $<"
The issue that I am having is with the order that I need things to run in. The command line call should tell make to use either debug or release, which sets a make variable, then call all. all should then run the pattern rule at the bottom before running the line currently in the all rule. So, how do I make a pattern rule a dependency and how do I call a rule from another rule?
Use target-specific variables
While not strictly necessary, separating your flags goes a long way in managing build options, you can then use target-specific variable appends to toggle the flags. While you're at it you might as well use the built-in variable names.
I've also added dependency generation (-MMD -MP) because it's always useful.
ODIR := obj
CDIR := src
HDIR := inc
SRCS := $(wildcard $(CDIR)/*.cpp)
OBJS := $(SRCS:$(CDIR)/%.cpp=$(ODIR)/%.o)
DEPS := $(OBJS:%.o=%.d)
CPPFLAGS := -I$(HDIR) -MMD -MP
CXXFLAGS := -std=c++11 -Wall -Wno-write-strings -Wno-sign-compare -pthread -O2
LDFLAGS := -pthread
LDLIBS := -lpaho-mqtt3c
NAME := tls_test
.PHONY: debug release clean
debug: CPPFLAGS+=-DDEBUG
debug: CXXFLAGS+=-g
release: CPPFLAGS+=-DRELEASE
debug release: $(NAME)
$(NAME): $(OBJS)
$(CXX) $(LDFLAGS) $^ $(LDLIBS) -o $#
$(OBJS): $(ODIR)/%.o: $(CDIR)/%.cpp
$(CXX) $(CXXFLAGS) $(CPPFLAGS) -c $(OUTPUT_OPTION) $<
clean: ; $(RM) $(NAME) $(OBJS) $(DEPS)
-include $(DEPS)