I am using modelsim. I wrote simple code but i am getting error.
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity clk_counter is
port(output : out bit;
clk : in bit
);
end clk_counter;
architecture rtl of clk_counter_arch is
signal clock_counter_output_flag: bit;
constant clock_max_count : integer := 20000;
begin
process (clock_counter_output_flag, clk,CLK'event )
variable clock_count : integer := 0;
--constant clock_max_count : integer := 20000;
variable clock_out : bit := 0;
-- wait until CLK'event and CLK='1';
begin
if (CLK'event and CLK='1') then
clock_count := clock_count+1;
if (clock_count = clock_max_count) then
clock_out := 1;
else
clock_out := 0;
end if
end if
clock_counter_output_flag <= clock_out;
end process;
END Architecture;
Error messege:
# ** Error: (vcom-11) Could not find work.clk_counter_arch.
#
# ** Error: C:/Modeltech_pe_edu_10.4a/examples/work/src/clk_counter(13): VHDL Compiler exiting
Your entity name is clk_counter and you have defined architecture rtl of clk_counter_arch. Hence, you are getting error. Change clk_counter_arch to clk_counter.
Second, you should end architecture as end rtl.
Also, why are you using two additional variables clock_out and clock_counter_output_flag ? If you want that values as output of your code, you should simply write
if (CLK'event and CLK='1') then
clock_count := clock_count+1;
if (clock_count = clock_max_count) then
output<='1';
else
output <='0';
end if;
end if;
Related
Trying to make a UART Transmitter to send a data from FPGA to PC; 9600 baudrate, 8-bits, no parity, 1 start & stop bit; I wrote a code with VHDL, run synthesis and simulate it in a way I like it to be. I wanted to see it with BASYS 3 FPGA, After created constraints, Run Implementation issued an error in which its called "Opt_Design Error".
library ieee;
use ieee.std_logic_1164.all;
entity rs232_omo is
generic(clk_max:integer:=10400); --for baudrate
port(
clk : in std_logic;
rst : in std_logic;
start : in std_logic;
input : in std_logic_vector(7 downto 0);
done : out std_logic;
output : out std_logic;
showstates: out std_logic_vector(3 downto 0)
);
end entity;
architecture dataflow of rs232_omo is
type states is (idle_state,start_state,send_state,stop_state);
signal present_state,next_state : states;
signal data,data_next : std_logic;
begin
process(clk,rst)
variable count : integer range 0 to clk_max;
variable index : integer range 0 to 10;
begin
if rst='1' then
present_state<=idle_state;
count:=0;
data<='1';
done<='0';
elsif rising_edge(clk) then
present_state<=next_state;
count:=count+1;
index:=index+1;
data<=data_next;
end if;
end process;
process(present_state,data,clk,rst,start)
variable count : integer range 0 to clk_max;
variable index : integer range 0 to 10;
begin
done<='0';
data_next<='1';
case present_state is
when idle_state =>
showstates<="1000";
data_next<='1';
if start='1' and rst='0' then
count:=count+1;
if count=clk_max then
next_state<=start_state;
count:=0;
end if;
end if;
when start_state =>
showstates<="0100";
data_next<='0';
count:=count+1;
if count=clk_max then
next_state<=send_state;
count:=0;
end if;
when send_state =>
showstates<="0010";
count:=count+1;
data_next<=input(index);
if count=clk_max then
if index=7 then
index:=0;
next_state<=stop_state;
else
index:=index+1;
end if;
count:=0;
end if;
when stop_state =>
showstates<="0001";
count:=count+1;
if count=clk_max then
next_state<=idle_state;
done<='1';
count:=0;
end if;
end case;
end process;
output<=data;
end architecture;
This's the error message in detail
"[DRC MDRV-1]Multiple Driver Nets:Net done_OBUF has multiple drivers:
done_OBUF_inst_i_1/O,and done_reg/Q"
"[Vivado_Tcl 4-78] Error(s) found during DRC. Opt_Design not run."
What would be the reason for this error?
You are assigning done both in the first and the second process, which is exactly what the implementation is complaining about, you cannot have multiple drivers.
Remove done<='0'; from the first process and it should complete the implementation.
(I didn't check if the rest of the code is doing exactly what you want.)
I am fairly new to VHDL and I am running some snippets from a code I was given to see what it is doing. There is a custom array type I want to see in the console, but I get and error when I try to write it.
entity hello_world is
end entity hello_world;
library STD;
library IEEE;
use IEEE.std_logic_1164.all;
use STD.textio.all;
use IEEE.std_logic_textio.all;
use IEEE.numeric_std.all;
architecture test of hello_world is
type row_type is array(0 to 2) of std_logic_vector(3 downto 0);
type new_type is array(0 to 1) of row_type;
signal max_new : new_type := (others => (others => (others => '0')));
begin
my_print : process is
variable my_line : line;
begin
write(my_line, string'("Value of max_new"));
write(my_line, max_new);
writeline(output, my_line);
wait;
end process my_print;
end architecture test;
The error I get while running the simulation is:
Error: type error near 'max_new': expected type 'std_ulogic'. Error: formal 'l' of mode inout must have an associated actual. Error: formal 'value' has no actual or default value. Error: indexed name prefix type 'void' is not an array type
If I understood correctly, row type is an array of size 3, in each position I have a vector made of 4 bits. new_type is an array of size 2, in each position I have a row_type, which is an array of size 3 with a 4 bits vector in each position. Is this correct? Since it is initialized to 0, I expect to see only that.
I am using Vivado 2018.3 for the simulation.
Any help would be highly appreciated!
You could also author your own write procedure:
entity hello_world is
end entity hello_world;
-- library STD;
library IEEE;
use IEEE.std_logic_1164.all;
use STD.textio.all;
use IEEE.std_logic_textio.all;
-- use IEEE.numeric_std.all;
architecture test of hello_world is
type row_type is array(0 to 2) of std_logic_vector(3 downto 0);
type new_type is array(0 to 1) of row_type;
signal max_new : new_type := (others => (others => (others => '0')));
procedure write (l: inout line; new_type_val: in new_type) is
begin
write (l, string'("("));
for i in new_type'range loop
write (l, string'("("));
for j in row_type'range loop
write (l, string'(""""));
write(l, new_type_val(i)(j));
write (l, string'(""""));
if j /= row_type'right then
write(l, string'(","));
end if;
end loop;
write (l, string'(")"));
if i /= new_type'right then
write(l, string'(","));
end if;
end loop;
write (l, string'(")"));
end procedure;
begin
my_print:
process is
variable my_line: line;
begin
write(my_line, string'("Value of max_new = "));
write(my_line, max_new);
writeline(output, my_line);
wait;
end process my_print;
end architecture test;
ghdl -r hello_world
Value of max_new = (("0000","0000","0000"),("0000","0000","0000"))
using preexisting write procedure overloads as building blocks.
You can also use type specific conversions to strings eliminating the dependence on Synopsys package std_logic_textio as well as introducing the ability to use report statements:
library ieee;
use ieee.std_logic_1164.all;
use std.textio.all;
architecture no_std_logic_textio of hello_world is
type row_type is array(0 to 2) of std_logic_vector(3 downto 0);
type new_type is array(0 to 1) of row_type;
signal max_new : new_type := (others => (others => (others => '0')));
-- For VHDL version < -2008:
function to_string (inp: std_logic_vector) return string is
variable image_str: string (1 to inp'length);
alias input_str: std_logic_vector (1 to inp'length) is inp;
begin
for i in input_str'range loop
image_str(i) := character'VALUE(std_ulogic'IMAGE(input_str(i)));
end loop;
return image_str;
end function;
function to_string (nt: new_type) return string is
variable l: line;
begin
write (l, string'("("));
for i in new_type'range loop
write (l, string'("("));
for j in row_type'range loop
write (l, '"' & to_string(nt(i)(j)) & '"');
if j /= row_type'right then
write(l, string'(","));
end if;
end loop;
write (l, string'(")"));
if i /= new_type'right then
write(l, string'(","));
end if;
end loop;
write (l, string'(")"));
return l.all;
end function;
begin
my_print:
process is
variable my_line: line;
begin
write (my_line, string'("value of max_new = "));
write(my_line, to_string(max_new));
writeline(output, my_line);
report LF & HT & "max_new = " & to_string(max_new);
wait;
end process my_print;
end architecture no_std_logic_textio;
And this demonstrates both writing to output and a report statement:
ghdl -r hello_world
value of max_new = (("0000","0000","0000"),("0000","0000","0000"))
hello_world.vhdl:95:9:#0ms:(report note):
max_new = (("0000","0000","0000"),("0000","0000","0000"))
The function write of std.textio can take the following arguments as value (https://www.hdlworks.com/hdl_corner/vhdl_ref/VHDLContents/TEXTIOPackage.htm) :
bit
bit_vector
boolean
character
integer
real
string
time
IEEE.std_logic_textio add std_logic and his derivated to this list but Array is not handled by write.
You can print your array like that :
my_print : process is
variable my_line : line;
begin
write(my_line, string'("Value of max_new"));
for I in 0 to 1 loop
for J in 0 to 2 loop
write(my_line, max_new(I)(J));
end loop;
end loop;
writeline(output, my_line);
wait;
end process my_print;
I'm writing a small VHDL process block and I wanted to assign a value to a variable if it hasn't been set yet. The input has no value at first, so I was wondering if there was something that could set new_ace to '0' if ace is still uninitialized or unknown.
entity rules is
port(
ace : in std_logic := '0'; --Tried setting 0 as default
ace_out : out std_logic
);
end rules;
architecture behavior of gA6_rules is
begin
cards: process(ace)
variable new_ace : std_logic := '0'; --Tried setting 0 as default
begin
if ace = 'U' or ace = 'X' then --Tried checking for unitialized
new_ace := '0';
else
new_ace := ace;
end if;
ace_out <= new_ace; --Next input will be this output
end process;
end behavior;
The problem is that when I simulate my design, it shows that ace_out is still undefined, even if I try setting it with := '0' or if I use the if statement.
I am trying to read an image file using textio package in vhdl.
If i open an .jpg with notepad , i will get some junk data but actually it is ASCII data . Here i am trying to read these ascii data and convert them into bytes.
below is my code:
library ieee;
use ieee.std_logic_1164.all;
use std.textio.all;
use ieee.std_logic_textio.all;
entity file_io is
port (
clk: in std_logic;
Data: out std_logic_vector(7 downto 0)
);
end entity;
architecture behav of file_io is
signal test_data : std_logic_vector(7 downto 0);
use ieee.numeric_std.all;
use std.textio.all;
use ieee.std_logic_textio.all;
begin
File_reader:process(clk)
file f : text open read_mode is "C:\Users\Public\Pictures\Sample Pictures\Chrysanthemum.jpg";
variable L: line;
variable var_int: integer:= 0;
variable var_char: character;
begin
if rising_edge(clk) then
while not endfile(f) loop
readline(f, L);
read(L, var_char);
var_int := character'pos(var_char);
test_data <= std_logic_vector(to_unsigned(var_int, test_data'length));
end loop;
end if;
Data <= test_data;
end process;
end architecture behav;
testbench:
LIBRARY ieee;
use ieee.std_logic_1164.ALL;
use std.textio.all;
ENTITY file_io_test IS
END file_io_test;
ARCHITECTURE behavior OF file_io_test IS
use work.io.all;
signal clk: std_logic := '0';
signal Data: std_logic_vector(7 downto 0);
-- Clock period definitions
constant clk_period : time := 10 ns;
BEGIN
-- Instantiate the Unit Under Test (UUT)
UUT:
entity work.file_io(behav)
port map (
clk => clk,
Data => Data
);
-- Clock process definitions( clock with 50% duty cycle is generated here.
clk_process :process
begin
clk <= '1';
wait for clk_period/2; --for 5 ns signal is '1'.
clk <= '0';
wait for clk_period/2; --for next 5 ns signal is '0'.
end process;
end behavior;
I am getting only one byte in waveform. expected result is : Every clock cycle new character should be rread and new byte should be obtained.
below is waveform:
below is the image I am trying to read:
You have a while loop placed inside the rising_edge part of your process. What happens is that when the first clock edge occurs, the while loop iterates until the end of the file and gives you the last byte of the input image.
Removing the while loop statement should solve your issue.
The question has a fundamental flaw. You can't use textio to read binary values, it's for text.
See IEEE Std 1076-2008 16.4 Package TEXTIO paragraphs 3 (in part) and 4:
Procedures READLINE, WRITELINE, and TEE declared in package TEXTIO read and write entire lines of a file of type TEXT. Procedure READLINE causes the next line to be read from the file and returns as the value of parameter L an access value that designates an object representing that line. If parameter L contains a non-null access value at the start of the call, the procedure may deallocate the object designated by that value. The representation of the line does not contain the representation of the end of the line. ...
The language does not define the representation of the end of a line. An implementation shall allow all possible values of types CHARACTER and STRING to be written to a file. However, as an implementation is permitted to use certain values of types CHARACTER and STRING as line delimiters, it might not be possible to read these values from a TEXT file.
And that can be demonstrated with your Chrysanthemum.jpg:
It is possible in VHDL to read raw characters one at a time (matching your need).
See IEEE Std 1076-2008 5.5 File types:
So all we have to do is declare a file type and we get these procedures defined implicitly.
We can use them to invoke raw read, without any end of line issues caused by textio:
library ieee;
use ieee.std_logic_1164.all;
entity file_io is
port (
clk: in std_logic;
Data: out std_logic_vector(7 downto 0);
done: out boolean
);
end entity;
architecture foo of file_io is
use ieee.numeric_std.all;
begin
File_reader:
process (clk)
-- "C:\Users\Public\Pictures\Sample Pictures\Chrysanthemum.jpg";
constant filename: string := "Chrysanthemum.jpg"; -- local to sim
variable char_val: character;
variable status: FILE_OPEN_STATUS;
variable openfile: boolean; -- FALSE by default
type f is file of character;
file ffile: f;
variable char_count: natural := 0;
begin
if rising_edge (clk) then
if not openfile then
file_open (status, ffile, filename, READ_MODE);
if status /= OPEN_OK then
report "FILE_OPEN_STATUS = " &
FILE_OPEN_STATUS'IMAGE(status)
severity FAILURE;
end if;
report "FILE_OPEN_STATUS = " & FILE_OPEN_STATUS'IMAGE(status);
openfile := TRUE;
else
if not endfile(ffile) then
read(ffile, char_val);
-- report "char_val = " & character'image(char_val);
char_count := char_count + 1;
Data <= std_logic_vector (
to_unsigned(character'pos(char_val),
Data'length) );
end if;
if endfile(ffile) then -- can occur after last character
report "ENDFILE, read " &
integer'image(char_count) & "characters";
done <= TRUE;
FILE_CLOSE(ffile);
end if;
end if;
end if;
end process;
end architecture foo;
library ieee;
use ieee.std_logic_1164.all;
entity file_io_test is
end file_io_test;
architecture behavior of file_io_test is
signal clk: std_logic := '0';
signal data: std_logic_vector(7 downto 0);
signal done: boolean;
constant clk_period: time := 10 ns;
begin
uut:
entity work.file_io(foo)
port map (
clk => clk,
data => data,
done => done
);
clk_process:
process
begin
if not done then
clk <= '1';
wait for clk_period/2;
clk <= '0';
wait for clk_period/2;
else
wait;
end if;
end process;
end architecture behavior;
Now we can have all the characters than can delimit a line show up in our read:
Note that package std.textio is not made visible through any context item.
I'm trying to write a simple vhdl code. When I run this code in quartus 2 there is no problem. However, when I run on modelsim, there is an error at line 2, that is error at "use ieee.std_logic_all.1164;" . I have no clue since I'm new to vhdl. By the way, i'm using Modelsim Starter edition 6.5e
library ieee;
use ieee.std_logic_all.1164;
entity tb is
end tb;
architecture behaviour of tb is
component ORG is
port (
a : in std_logic;
b : in std_logic;
c : out std_logic;
);
signal ina, inb, outc : std_logic;
constant period : time := 100ns;
signal done : boolean := false;
begin
process
begin
ina = '0';
inb = '0';
wait for period;
ina = '1';
inb = '0'
wait for period;
done <= true;
wait;
end process;
end behaviour;
You have a number of problems in your code that will cause syntax errors.
As #rene pointed out, the library name is std_logic_1164 - you have "1164" and "all" reversed (the capitalization of IEEE isn't significant).
There should not be a semicolon at the end of the c port line
You should include an end component; statement after the port declaration (that is, after the closing parenthesis and semicolon)
The equals signs in the process should be <=
Finally, there should be a space between 100 and ns