I am trying to learn how to compile using gcc/makefile
If I use the makefile below everything works.
all:
g++ .\src\hello.cpp -o helloworld
But What I would like is to specify the source folder and files.
INCLUDEPATHS= \
-I".\src\"
CFLAGS= -Wall -g $(INCLUDEPATHS)
all:
helloworld
But that does not seem to work, the error I get is
make all
make: *** No rule to make target `hello.exe', needed by `all'. Stop.
How do I change my makefile to have the include path defined?
Related
I am very new to Makefile. I had build the following makefile(Which don't work).I wan't put genarated object codes in differnt folder(the folder is in current directory).
$ ls
main.cpp Makefile object_code Time.cpp Time_.h
how can I do this ??
VER = Debug
CC = g++
OBJECTFIELS = ./object_code/main.o ./object_code/Time.o
../$(VER)/main: $(OBJECTFIELS)
$(CC) $(OBJECTFIELS) -o $#
$(OBJECTFIELS): Time_.h
./object_code/main.o: main.cpp
./object_code/Time.o: Time.cpp
clean:
rm $(OBJECTFIELS) main
this is error.
$ make
g++ ./object_code/main.o ./object_code/Time.o -o ../Debug/main
g++: error: ./object_code/main.o: No such file or directory
g++: error: ./object_code/Time.o: No such file or directory
g++: fatal error: no input files
compilation terminated.
Makefile:8: recipe for target '../Debug/main' failed
make: *** [../Debug/main] Error 1
please this is last question.
I don't see how you can possibly get that output given the makefile you've posted here.
Either the object files already exist in which case the link will succeed rather than printing that error.
Or the object files don't exist in which case make will complain because it doesn't know how to make them. There must be some difference between the makefile you're using and the one you've posted here.
In any event, make knows how to build a file foo.o from a file foo.cpp for any string foo. There's a built-in rule that tells it how to do that.
But, make doesn't know how to build a file ./object_code/foo.o from a file foo.cpp, regardless of foo. There's no built-in rule that tells make how to build object files in some random other directory. If you want make to do that, you'll have to tell it how. You should remove the lines:
./object_code/main.o: main.cpp
./object_code/Time.o: Time.cpp
and replace them with a pattern rule describing how to build object files into the object_code directory (I'm using CXX as the compiler variable here: by convention CC is the C compiler and CXX is the C++ compiler, and you should always stick with convention unless there's a good reason not to):
VER = Debug
CXX = g++
OBJECTFIELS = ./object_code/main.o ./object_code/Time.o
../$(VER)/main: $(OBJECTFIELS)
$(CXX) $(OBJECTFIELS) -o $#
$(OBJECTFIELS): Time_.h
./object_code/%.o : %.cpp
$(CXX) -c -o $# $<
clean:
rm $(OBJECTFIELS) main
This is how my directory looks like:
/project
makefile
/ceda_lib
makefile
files....
/general
makefile
files....
/CLI
makefile
files....
/objects
files.o
Makefile(main):
1 #start other makefiles
2
3
4 o= ./objects
5 DEPS= Affine.hpp CEDA.hpp generalParameters.hpp generalFunctions.hpp
6 OBJ= $o/main.o $o/Affine.o $o/generalFunctions.o
7 CC=g++
8 CFLAGS= -Wall -g -I.
9 export CC
10 export CFLAGS
11 export DEPS
12
13 all:
14 ▸---+$(MAKE) -C general
15 ▸---+$(MAKE) -C ceda_lib
16 ▸---+$(MAKE) -C CLI
17
18 run: $(OBJ) $(DEPS)
19 ▸---$(CC) -o $# $^
The other makefiles look like this:(update2)
1 include ../makefile.variables
2
3 OBJ = main.o
4 all: $(OBJ)
5
6 $(OBJ): %.o: %.cpp $(DEPS)
7 ▸---$(CC) -o ../objects/$# -c $< $(CFLAGS)
What I want to do is for all code in the 3 directories to be compiled and all objects to be stored in the /object directory. Then an executable will be created from the $DEPS and the contents of /object directory.
This makefile doesn't work sadly. Could you please find what I've done wrong and also could you suggest me ways to improve the code. (I'm quite new to makefiles).
Also this is the output whenever I try making the project:(Update2)
make: Entering directory '/home/george/Documents/CEDA'
make -C general
make[1]: Entering directory '/home/george/Documents/CEDA/general'
g++ -o ../objects/generalFunctions.o -c generalFunctions.cpp -Wall -g -I.
make[1]: Leaving directory '/home/george/Documents/CEDA/general'
make -C ceda_lib
make[1]: Entering directory '/home/george/Documents/CEDA/ceda_lib'
g++ -o ../objects/Affine.o -c Affine.cpp -Wall -g -I.
Affine.cpp:4:33: fatal error: generalParameters.hpp: No such file or directory
#include "generalParameters.hpp"
^
compilation terminated.
makefile:7: recipe for target 'Affine.o' failed
make[1]: *** [Affine.o] Error 1
make[1]: Leaving directory '/home/george/Documents/CEDA/ceda_lib'
makefile:8: recipe for target 'All' failed
make: *** [All] Error 2
make: Leaving directory '/home/george/Documents/CEDA'
This is the makefile.variables
1 #variables used by all makefiles in project directory
2
3 PATH_TO_DIR = ~/Documents/CEDA
4 c = $(PATH_TO_DIR)/ceda_lib
5 g = $(PATH_TO_DIR)/general
6 e = $(PATH_TO_DIR)/CLI #e for executable
7
8 DEPS= $c/Affine.hpp $c/CEDA.hpp $g/generalParameters.hpp $g/generalFunctions.hpp
9 CC=g++
10 CFLAGS= -Wall -g -I.
Here:
OBJ= main.o
../objects/%.o: %.cpp $(DEPS)
$(CC) -c $< $(CFLAGS)
This makefile contains one rule, which is a pattern rule, a way to build any file with a name like ../objects/foo.o. But it doesn't tell Make which object file it is to build. To be precise, a pattern rule cannot be the default rule.
The simplest way to fix this is with the addition of an ordinary rule:
../objects/$(OBJ):
Once you have this working you will have the object files, but there are still problems in the main makefile. The run rule will not build an executable, and if you want to execute that rule you will have to invoke it on the command line, it won't follow automatically.
You are attempting recursive use of Make -- which is tricky -- before you've mastered the basics. I suggest you try using the makefile to build the object files, then try to build the executable using the command line, then look carefully at the command you used and rewrite the run rule.
Once you get that far, other improvements are possible. (Make is a powerful tool, but it has a long learning curve.)
EDIT: If it isn't working at all, try something simpler first.
Pick a source file in ceda_lib, like, I don't know main.cpp. Verify that the source file exists and that the corresponding object file (main.o) does not. Edit the makefile (in ceda_lib/) to this:
main.o: main.cpp
$(CC) -c $< $(CFLAGS)
Then within ceda_lib/, try make and see what happens.
If it builds main.o, then delete main.o, and then from project/ try make -C ceda_lib, and see what happens. If that builds ceda_lib/main.o, then we can move on to more advanced makefiles.
I am having trouble compiling using make in windows 7 with gcc and the gsl library. It occurs only when using make (when I type the compilation commands manually into the cmd line, it compiles correctly). I found some posts where people had similar errors from gcc, but none where it worked when typing normally, but not when using make. The contents of my Makefile are shown below:
#Compiler
COMP=gcc
# Compiler Flags. -Wall turns on all warnings
FLAGS=-Wall
# GSL include file dir
INCLUDES=GnuWin32/include
# GSL Libraries directory
LIB=GnuWin32/lib
# Library Flags
LFLAGS=-lgsl -lgslcblas -lm
# Target Program
EXE=ex2.1.exe
# Dependencies needed for $(PROGRAM)
OBJ=ex2.1.o
# List of source files for objects
SRC=ex2.1.c
# List with types of files to be cleared by clean:
TRASH=*.exe *.o
# I/O files to be cleaned with 'very clean' target
#IOFILES= *.dat *.out *.csv *.mod
all: $(SRC) $(EXE)
$(EXE): $(OBJ)
$(COMP) -L/$(LIB) $(OBJ) $(LFLAGS) -o $(EXE)
$(OBJ): $(SRC)
$(COMP) -I/GnuWin32/include -c ex2.1.c
#$(COMP) -I/$(INCLUDES) -c $(SRC)
clean:
del $(TRASH)
If I type make with only the ex2.1.c present in the directory, I get the following output and error:
gcc -I/GnuWin32/include -c ex2.1.c
gcc: error: CreateProcess : No such file or directory
make: *** [ex2.1.o] Error 1
However, if I first type "gcc -I/GnuWiun32/include -c ex2.1.c", ex2.1.o is created successfully with no error. If then type 'make' I get the following output/error:
gcc -L/GnuWin32/lib ex2.1.o -lgsl -lgslcblas -lm -o ex2.1.exe
gcc: fatal error: -fuse-linker-plugin, but liblto_plugin-0.dll not found
compilation terminated
make: *** [ex2.1.exe] Error 1
But if I manually enter "gcc -L/GnuWin32/lib ex2.1.o -lgsl -lgslcblas -lm -o ex2.1.exe" then the executable compiles and runs like it should, so the problem seems to be with how make is calling gcc? My PATH variable contains the paths to both make.exe as well as gcc.exe, so I am not sure what I do not set up correctly. Does anyone have an idea of what may be wrong? Thanks.
I'm currently writing a makefile that is able to compile different targets (Like Debug, Development, Release). The linking and compiling rules look like that:
$(DEVELOPMENT_OUT): $(subst rep,development,$(OBJS))
g++ -o $(DEVELOPMENT_OUT) $(subst rep,development,$(OBJS))
obj/development/%.o: src/%.cpp
g++ -c -MMD -MP -MF"$(#:%.o=%.d)" -MT"$(#:%.o=%.d)" -o "$#" "$<"
Now, I get this output:
make: *** No rule to make target 'obj/development/Main.o', needed by 'bin/Development.exe'. Stop.
But shouldn't the pattern rule apply for the Main.o?
I use GNU Make 3.82.90 of MinGW.
There's not enough information here to say why it doesn't work. If you're sure you have a file src/Main.cpp then make should choose that rule. Is the cpp file a source file, or a generated file? If it's generated then maybe the real problem is lower down, where the generating happens. You can try using make -d to see what make is doing and why it doesn't like this rule.
I keep getting this error:
make: *** No rule to make target `all'. Stop.
Even though my make file looks like this:
CC=gcc
CFLAGS=-c -Wall
all: build
build: inputText.o outputText.o main.o
gcc main.o inputText.o outputText.o -o main
main.o: main.c
$(CC) $(CFLAGS) main.c -o main.o
inputText.o: inputText.c
$(CC) $(CFLAGS) inputText.c -o inputText.o
outputText.o: outputText.c
$(CC) $(CFLAGS) outputText.c -o outputText.o
Yes there should be a tab space underneath the target and there is in my make file.
I can get it to work if I try one of the targets like main.o, inputText.o and outputText.o but can't with either build or all.
EDIT:
I just randomly tried running make and telling it the file using the following command:
make -f make
This works but why doesn't just typing make work?
Your makefile should ideally be named makefile, not make. Note that you can call your makefile anything you like, but as you found, you then need the -f option with make to specify the name of the makefile. Using the default name of makefile just makes life easier.