I have used sfixed signals, using the ieee_proposed library in my design.
My design works fine, but now I want to create Schematic Symbol from ISE14.7(Under Design Utilities). I am getting an error saying that ieee_proposed is not found.
How can I resolve this error?
Related
When I edit a VHDL testbench (simulation source) in Vivado (project mode), background syntax checking seems to be disabled: Obvious syntax errors like missing semicolons or undefined signals are not underlined with a squiggly red line (as in all design sources).
Is there a way to activate automatic background syntax checking for test benches? Could there be another reason why some files are not syntax-checked?
This seems to be missing feature:
Xilinx Forums: No-syntax-highlighting-for-VHDL-testbenches
I recently posted something with relation to this assignment but I have hit another stumbling block and can't seem to find the solution. I have got a 4 bit alu simulating but I am required to use a pre-written test bench provided to me by the teacher. I have imported the test bench file and un selected the check mark next to synthesis in the source file properties as instructed.
My unit under test as detected by the testbench source file is the entity .vhd file of my project and so all should be fine except that when I simulate the program it just simulates as per normal with no output in the tcl console regarding any of the assertions of which the testbench is composed.
I have obviously googled and got more instructions about how to do this but I couldn't get specific instructions for the vivado software. It talked about xilinx and there being a process window, which is nowhere to be seen in Vivado. I can't understand why this so seemingly simple thing is taking me so long to figure out. There aren't any syntax errors and it says in the messages near the compiler window that the testbench is being parsed. Here is a screenshot of my file structure in the vivado IDE.
Can anyone please tell me how to do this?
Thanks,
Simon.
When you simulate, it will use whatever is set as the top level simulation entity as the top level for that simulation. In your image, the test bench is selected in the project hierarchy, but the UUT is set as the top module. You need to right click your test bench, and choose 'Set as Top'.
It seems that i have some problems with the Activ-HDL student edition. When I want to compile the following error appears:
# Error: VLM_0040: VHDL unit cannot be compiled as the target library name is not a legal VHDL identifier.
I don't know why because yesterday I installed it and today I have this error. Can someone help me.
As far as I understand, when you compile your sources they are added to a library that has the same name as your Active-HDL design, and, as the error message suggests, if that name doesn't fall under VHDL identifier naming conventions you get the aforementioned error.
To give your design a proper name you should follow several simple rules:
Names (or identifiers) may consist of letters, numbers and
underscore.
Names must start with a letter.
None of the VHDL keywords (i.e. signal, bus, component, wait, etc.) may be reused as a name.
To add to the (correct) answer above: the name of the library that your sources are added to is shown in the Design Browser below "Add New Library" (see image, where the library is called "hy-phen").
This name can be changed by clicking "Add new Library". By right-clicking the new library you can set it as active. Now the source code should compile into the new library (without renaming the whole Active-HDL design).
After setting the new library as active, the old one (with the invalid name) can be detached from the project (by right-clicking on it).
I am trying to use fixed point numbers in my VHDL project, but I keep having trouble implementing the library (found here http://www.eda-stds.org/fphdl/fixed_pkg_c.vhdl). The error I receive when trying to simulate is this
<ufixed> is not declared
My question is how exactly should a library be implemented so it can be used? As of now I have added it to the project in the IEEE_PROPOSED library, but it is not working. All source code can be found here https://github.com/srohrer32/beamformer/tree/fixed_num, under the hdl folder and libraries folder.
Are you using modelsim? Are you using a project? If not... I find the best way is to first compile the library on its own. Open your modelsim.ini file and make a path to the library. Like this:
lib_test = c:/test/source/lib_test
Finally, compile your own code and make sure you use the -modelsimini switch on vcom modelsim command.
If you are using a project (which I don't like, they are not as flexible) then you can point the project to the library.
More help about modelsim compiling with commands:
http://www.tkt.cs.tut.fi/tools/public/tutorials/mentor/modelsim/getting_started/gsms.html#compiling
Not being an isim user myself, a search through the ISim User Guide implies you need to create a separate project to compile into a library, contrasting with how easy it is to target a library from the command line.
Presumably you'd also need to add the library as a resource in your project. Funny there are no complaints about that yet you have:
library ieee_proposed;
in delay_calculation.vhd, noting that a library declaration simply makes the name available. Somewhere the implementation dependent mapping for the library name to library needs to be made. This by default is in xilinxisim.ini, but I imagine your project management interface allows you to map the library into your project, and isim should know where to look for the library.
Nosing around the user guide may be worthwhile.
In Simulation Steps Overview
User Libraries
Depending upon how you launch ISim, there are different methods
available to add user libraries:
When launching Project Navigator, define the user libraries in the ISE tool. See “Working with VHDL Libraries” in ISE Help for
details.
When using ISim standalone, interactive command mode, or non-interactive mode, set the library mapping file (see Appendix A,
Library Mapping File (xilinxisim.ini) to point to your logical or
physical libraries.
When launching ISim from the PlanAhead tool, define the user libraries in that tool. See the PlanAhead User Guide (UG632) for more
information. Appendix D, Additional Resources, contains a link to the
document.
See Working with VHDL Libraries, see To Create a VHDL Library and To Add Files to a VHDL Library.
(The top level link to ISE Help).
You'd think there'd be a FAQ for those of us apostate - speed reading 'religious' tomes sucks even using Google to find them. Notice the explanations are in terms of menu pull down actions, analogous to command line entry. We're being bitten by what's available on the top menu bar. And when you do manage to add and use a library successfully you'll remember how until someone changes the menus around, and you could of course wonder about documentation lagging.
Presumably what you've tried to do is set up the library mapping for synthesis mode in the ISE GUI, which is straightforward but completely ignored by iSim since it has its own system for managing library mappings. I'm not an iSim user but after looking at the documentation and a little testing it looks like the easiest way to set up a library is from the command line:
# This creates an ieee_proposed directory with a partially compiled object.
vhpcomp --work ieee_proposed=ieee_proposed fixed_pkg_c.vhdl
# Add a mapping from the logical library to the physical path.
# *nix shown. Windows would be similar or just use a text editor.
# <logical name>=<physical path>
echo ieee_proposed=`pwd`/ieee_proposed >> path/to/your/xilinxisim.ini
Make sure the xilinxisim.ini file is visible to iSim and it should pick up the mapping to your compiled library. You should be able to keep running vhpcomp from the parent of ieee_proposed to add more files to the library. You may have to manually copy the system default version to maintain the standard library mappings.
I was trying to generate a netlist from a simple Model in simulink. I can run the simulation (using sysgen).
When I try to create a netlist , it throws an error :
"
* ERROR *
Errors occurred during netlist
generation. Error using ==>
xlProcBlockElaborateBMM at 19 synopsis
file 'C:\<..>\timing\synopsis' not
found "
So, I tried to create a synopsis folder manually, and then It started throwing following error:
* ERROR *
Errors occurred during netlist
generation. Java exception occurred:
com.xilinx.sysgen.netlist.NetlistInternal:
java.io.FileNotFoundException:
C:\Kiran\timing\synopsis\synopsis
(Access is denied)
at com.xilinx.sysgen.netlist.XTable.valueOf(Unknown
Source)
at com.xilinx.sysgen.netlist.Block.fromXTable(Unknown
Source)
I tried running Matlab as Administrator, but with same outcome. Kindly let me know if I am missing something here:
So, here are the config details :
Matlab version : Version 7.10 (R2010a)
Xilinx System Generator Version 12.2
I did not find any solutions in the Xilinx forums, so I am posting it here.
Thanks
Not come across that one - it sounds like a horrible internal error.
It looks like you're creating a timing netlist - can you create any of the other option netlists? It might provide different (more useful) error messages!
Other solutions are of the typically tedious form:
Re-run the Xilinx System Generator Configurator
try a different PC
reinstall the Xilinx tools
Log a WebCase
Sorry!