I am attempting to create an array of vectors in VHDL however I am getting an error in modelsim.
I have:
type read_data_array is array (0 to 73) of std_logic_vector(7 downto 0);
signal reg_data_stream : read_data_array;
I store data into the array by:
reg_data_stream(counter) <= read_data;
"read_data" is that of std_logic_vector(7 downto 0) and "counter" is a basic counter that increments from 0.
To index an array or a vector, VHDL expects an integer. If counter is a std_logic_vector, try:
to_integer(unsigned(counter)) <= read_data;
Related
In SystemVerilog I can create a multidimensional array as follows:
reg [31:0] mem[0:127];
However, in VHDL all of the examples for create a similar multidimensional arrays online in the VHDL book show that I must first create a type before creating the array. Example:
type mem_t is array(0 to 127) of std_logic_vector(31 downto 0);
signal mem :mem_t;
Is it possible to do this all in one step in VHDL like in verilog without first creating a type for the array? Example:
signal mem :array(0 to 127) of std_logic_vector(31 downto 0);
--syntax error:GHDL: Type mark expected in a subtype indication
--syntax error:vsim: near "array": (vcom-1576) expecting STRING or IDENTIFIER or << or '('
The reason why i'm asking is because i'm trying to avoid the use of a package to declare an array type, when connecting IO with an array that is connected between to modules in VHDL.
What you created is an array of an array - which is in general what you want. What #Matthew Taylor created is a multidimensional array.
WIth VHDL-2008 the elements of a composite can be unconstrained, and hence, you can create:
type std_logic_aoa is array (natural range <>) of std_logic_vector;
Realistic speaking this should be in a standard library - it is just not there currently.
And then you can use it by doing:
signal mem : std_logic_aoa (0 to 127)( 31 downto 0);
The reason you want an array of an array here is it allows you to do things like:
signal Data : std_logic_vector(31 downto 0) ;
. . .
Data <= mem(15) ;
No. It isn't.
It is possible to create genuinely multi-dimensional arrays in VHDL, but you still need to create a new type. That is the VHDL way. So, you'll still need your package.
Here's a multi-dimensional constrained array:
type c_mem_t is array (0 to 127, 31 downto 0) of std_logic;
and here's a multi-dimensional unconstrained array:
type mem_t is array (natural range <>, natural range <>) of std_logic;
And you use them like this:
signal mem : c_mem_t;
signal mem : mem_t(0 to 127, 31 downto 0);
In VHDL-2002 either both dimensions must be constrained or both must be unconstrained. In VHDL-2008, you can have one constrained and one not:
type mem_t_2008 is array (natural range <>, 31 downto 0) of std_logic;
I have declared an array
type REG_TYPE is array(0 to FIR_ORDER - 1) of
signed(DATA_WIDTH + COEFF_WIDTH - 1 downto 0)
and a signal temp of this type:
signal temp: REG_TYPE;
To meet the objective, I need to use adders and multipliers. On applying certain logic, I'm facing a situation where I need to call an adder whose result is a STD_LOGIC_VECTOR to be mapped to temp of type REG_TYPE.
This leads to an error. How to proceed?
type matrixsignal is array (LEVELS downto 0) of std_logic_vector(NBIT-1 downto 0);
signal p_matrix, g_matrix: matrixsignal;
signal col_temp_g, col_temp_p : std_logic_vector(LEVELS downto 0);
...
col_temp_p<=p_matrix(LEVELS downto 0)(j-1);
col_temp_g<=g_matrix(LEVELS downto 0)(j-1);
Hello everyone!
I want to select and copy the entire column (j-1) of the 2 arrays...but the compiler tells me that this way is not the correct one.
How is it possible to do it?
P.S. LEVELS,NBIT,j are initialized parameters...I did not report their initialization.
You should define matrixsignal as a 2-dimensional array instead of a one-dimensional array that nests another 1-dimensional array.
type matrixsignal is array(LEVELS downto 0, NBIT - 1 downto 0) of std_logic;
The PoC-Library offers that type as T_SLM (std_logic_matrix) together lot's of manipulation functions and procedures in package PoC.vectors. E.g. PoC defines a get_col function like this:
function get_col(slm : T_SLM; ColIndex : natural) return std_logic_vector is
variable slv : std_logic_vector(slm'range(1));
begin
for i in slm'range(1) loop
slv(i) := slm(i, ColIndex);
end loop;
return slv;
end function;
Usage:
subtype matrixsignal is T_SLM(LEVELS downto 0, NBIT - 1 downto 0);
signal p_matrix, g_matrix : matrixsignal;
signal col_temp_g, col_temp_p : std_logic_vector(LEVELS downto 0);
...
col_temp_p <= get_col(p_matrix, j - 1);
col_temp_g <= get_col(g_matrix, j - 1);
The package PoC.vectors can be synthesized.
Further functions are provided like:
slicing a complete row
slicing sub matrixes
flattening / serialization
creating matrix from vector / deserialization
overloaded boolean operators
row / column assignment
matrix merging
conversion to/from 1-dimensional array types containing another 1-dimensional array type
...
My purpose of this code is a cross total of a std_logic_vector.
I have the following code:
generic(
lowPass_len : integer := 4;
...
signal inputbuffer : std_logic_vector(lowPass_len-1 downto 0);
signal sum: integer range 0 to lowPass_len;
signal lowpass_alarm_tog : std_logic;
...
inputbuffer <= inputbuffer(lowPass_len-1 downto 1) & alarm_tog_d2_meta;
for i in (lowPass_len-1) downto 1 loop
sum <= to_integer(unsigned(inputbuffer(i-1)) + unsigned(inputbuffer(i)));
end loop;
because inputbuffer is a std_logic_vector, I wanted to cast it to unsigned to make the addition. then convert it to integer, as sum has this kind of type.
ghdl gives me the following mistake for two times in this line
conversion not allowed between not closely related types
The expression inputbuffer(i-1) just returns a single bit of type std_logic. This cannot be directly casted to unsigned because the latter is an array of std_logic.
You have to extend the single bit to a vector of the required length first. The length depends on the highest number which could be encountered in the addition.
We have a type which is an array of 32 bit "std_logic_vector" of size 3, which is defined in the following way:
subtype scalar is std_logic_vector(31 downto 0);
type vector_nd is array (natural range <>) of scalar;
subtype vector_3d is vector_nd(2 downto 0);
We have a signal of type "vector_3d" which we want to multiply by 2 and put the result in a signal of type "scalar":
signal v_normal_out_sig := vector_3d;
signal mult1_in1_sig := scalar;
--...
mult1_in1_sig <= 2*signed(v_normal_out_sig(0)) when cau_state = st_cycle18;
When we compile it we get the error:
No feasible entries for infix operator "*".
What is the right way to implement what we want? We are using the following libraries:
ieee.std_logic_1164.all
ieee.std_logic_arith.all
ieee.std_logic_unsigned.all
What we did eventually is the fallowing:
mult1_in1_sig <= v_normal_out_sig(0)(31) & v_normal_out_sig(0)(29 downto 0) & '0' when cau_state = st_cycle18;
And test gave the right results for both positive and negative numbers.