I have declared an array
type REG_TYPE is array(0 to FIR_ORDER - 1) of
signed(DATA_WIDTH + COEFF_WIDTH - 1 downto 0)
and a signal temp of this type:
signal temp: REG_TYPE;
To meet the objective, I need to use adders and multipliers. On applying certain logic, I'm facing a situation where I need to call an adder whose result is a STD_LOGIC_VECTOR to be mapped to temp of type REG_TYPE.
This leads to an error. How to proceed?
Related
I am trying to take this signal :
signal Fx3_bridge : std_logic_vector (1 downto 0);
To this output port:
Fx3_A : out std_logic;
I also want to discard the less significant bit of my logic vector.
A std_logic_vector is an array. Your std_logic_vector
signal Fx3_bridge : std_logic_vector (1 downto 0);
has two elements - 1 and 0. You index arrays in VHDL using brackets, so the most significant bit (strictly speaking: the left hand element) is
Fx3_bridge(1)
So, you want something like:
Fx3_A <= Fx3_bridge(1);
I want to have a loop that runs the all lines of my code and also that runs every position of all lines.
My problem is in selecting the line that the loop will run, and I want to have simple way to do it without making to write every single line one-by-one, cause the final code will have 66 lines to scan.
Hope you can help me.
Entity of this code will have 66 lines, but I'm just testing it this 10 lines right now:
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity lshift is
port( RED_Buffer1 : in std_logic_vector(6 downto 0);
RED_Buffer2 : in std_logic_vector(6 downto 0);
RED_Buffer3 : in std_logic_vector(6 downto 0);
RED_Buffer4 : in std_logic_vector(6 downto 0);
RED_Buffer5 : in std_logic_vector(6 downto 0);
IR_Buffer1 : in std_logic_vector(6 downto 0);
IR_Buffer2 : in std_logic_vector(6 downto 0);
IR_Buffer3 : in std_logic_vector(6 downto 0);
IR_Buffer4 : in std_logic_vector(6 downto 0);
IR_Buffer5 : in std_logic_vector(6 downto 0);
output : out bit_vector(1 downto 0));
end lshift;
What I have done so far but with no success:
ARCHITECTURE main OF lshift IS
SIGNAL condition1: boolean;
signal valor : std_ulogic;
BEGIN
PROCESS(IR_Buffer5)
BEGIN
FOR I IN 1 TO 5 LOOP
FOR J IN 1 TO 5 LOOP
CONSTANT linha_cond : string(1 to 12) := string(("RED_Buffer") && I);
IF (linha_cond(J) = '1') THEN
output <= "01";
END IF;
END LOOP;
END LOOP;
END PROCESS;
END main;
The purpose of this answer is to demonstrate indexing the subelement values of RED_Buffer1 through RED_Buffer5. Without the purpose of the code being revealed this could easily prove to be an XY Problem question.
While it is possible to organize RED_Buffer1 through RED_Buffer5 into a value that can be indexed as shown below, there are other issues as well.
library ieee;
use ieee.std_logic_1164.all;
entity lshift is
port (
red_buffer1: in std_logic_vector (6 downto 0);
red_buffer2: in std_logic_vector (6 downto 0);
red_buffer3: in std_logic_vector (6 downto 0);
red_buffer4: in std_logic_vector (6 downto 0);
red_buffer5: in std_logic_vector (6 downto 0);
ir_buffer1: in std_logic_vector (6 downto 0);
ir_buffer2: in std_logic_vector (6 downto 0);
ir_buffer3: in std_logic_vector (6 downto 0);
ir_buffer4: in std_logic_vector (6 downto 0);
ir_buffer5: in std_logic_vector (6 downto 0);
output: out bit_vector (1 downto 0)
);
end entity lshift;
architecture indexed_array of lshift is
signal condition1: boolean;
signal valor: std_ulogic;
type lbuffer is array (1 to 5) of std_logic_vector (6 downto 0);
signal red_buffer: lbuffer;
begin
red_buffer <= (red_buffer1, red_buffer2, red_buffer3, red_buffer4,
red_buffer5);
process (red_buffer)
begin
for i in 1 to 5 loop
for j in red_buffer'range loop
if red_buffer(i)(j) = '1' then
output <= "01";
end if;
end loop;
end loop;
end process;
end architecture indexed_array;
How the indexing is implemented here
A composite type (lbuffer) having the requisite number of elements with required element subtype is declared. This is possible because the declarations for ports RED_Buffer1 through RED_Buffer5 share a common subtype indication. Assignment to elements of an object of the type lbuffer would be compatible, having matching elements between the target and right hand expression.
A signal red_buffer with a type mark of lbuffer is declared.
A concurrent assignment was made to the signal in a concurrent signal assignment statement in the architecture statement part from an aggregate. The association in the aggregate is positional. It could as easily use named association:
-- red_buffer <= (red_buffer1, red_buffer2, red_buffer3, red_buffer4,
-- red_buffer5);
red_buffer <= (1 => red_buffer1, 2 => red_buffer2, 3 => red_buffer3,
4 => red_buffer4, 5 => red_buffer5);
The type of the aggregate is taken from context, here the assignment statement where red_buffer has the subtype lbuffer.
A selected element of the composite red_buffer is selected by an index name (red_buffer(i)). A subelement of red_buffer(i) is selected by use of an indexed name where the name red_buffer(i) where 'iis a constant using 'j from the inner loop - red_buffer(i)(j).
Note the range of the j parameter doesn't match the index range of subtype of the lbuffer element subtype here identical to the subtype of RED_Buffer1 through RED_Buffer5. This signifies a further potential semantic issue with the original code, whose purpose isn't made clear here. The only hint present in the original code comes from linha_cond where linha means line in Portuguese or Catalan indicating j is used to index within a 'line'.
The original code fails for two reasons
First an object can't be declared inline in VHDL. The for loop parameter is dynamically elaborated from an implicit declaration, the loop parameter is only visible within the loop statement's sequence of statements. The syntax doesn't allow for additional object declarations.
Second a name for a object declaration is conveyed in an identifier list consisting of one or more identifiers which are lexical elements (lexemes) that cannot be manipulated programmatically.
Other semantic issues with the question's code
The assignment to output without the passage of time doesn't appear useful.
A process statement is an independently executing concurrent statement wherein the loop statement containing an assignment to the same signal output will overwrite the projected output waveform for elements of output without any intervening passage of time.
There's only one entry in a projected output waveform queue for any particular simulation time. A simulation cycle consists of signal updates followed by the resumption and subsequent suspension of any processes sensitive to signal updates. The purpose is to emulate parallelism in hardware while describing behavior with sequential statements.
Here that would mean output would be updated to the value "01" if any of the if statement conditions in the unrolled loops evaluate to TRUE. That's likely not the intended behavior (without more information from the original poster).
Also note there is no output assignment to a different value and no default or otherwise assigned value. For synthesis this would represent a hold over delay on output until a '1' is first found.
In both cases this refers to an implicit latch for output.
This issue with the sample code can't be addressed without knowing how it is supposed to work and the only hint that has been shown here on Stackoverflow to date is by a question deleted by the user requiring 10K+ reputation to access (others will see aPage not found message, see revision 1).
Also concepts conveyed from programming or scripting languages don't generally port to Hardware Description Languages which are generally formal notations defined self-referentially (here in IEEE Std 1076, the VHDL Language Reference Manual) requiring inculcation or persistent effort to learn. HDLs generally describe hardware behaviorally and structurally not by programmatic equivalence.
type matrixsignal is array (LEVELS downto 0) of std_logic_vector(NBIT-1 downto 0);
signal p_matrix, g_matrix: matrixsignal;
signal col_temp_g, col_temp_p : std_logic_vector(LEVELS downto 0);
...
col_temp_p<=p_matrix(LEVELS downto 0)(j-1);
col_temp_g<=g_matrix(LEVELS downto 0)(j-1);
Hello everyone!
I want to select and copy the entire column (j-1) of the 2 arrays...but the compiler tells me that this way is not the correct one.
How is it possible to do it?
P.S. LEVELS,NBIT,j are initialized parameters...I did not report their initialization.
You should define matrixsignal as a 2-dimensional array instead of a one-dimensional array that nests another 1-dimensional array.
type matrixsignal is array(LEVELS downto 0, NBIT - 1 downto 0) of std_logic;
The PoC-Library offers that type as T_SLM (std_logic_matrix) together lot's of manipulation functions and procedures in package PoC.vectors. E.g. PoC defines a get_col function like this:
function get_col(slm : T_SLM; ColIndex : natural) return std_logic_vector is
variable slv : std_logic_vector(slm'range(1));
begin
for i in slm'range(1) loop
slv(i) := slm(i, ColIndex);
end loop;
return slv;
end function;
Usage:
subtype matrixsignal is T_SLM(LEVELS downto 0, NBIT - 1 downto 0);
signal p_matrix, g_matrix : matrixsignal;
signal col_temp_g, col_temp_p : std_logic_vector(LEVELS downto 0);
...
col_temp_p <= get_col(p_matrix, j - 1);
col_temp_g <= get_col(g_matrix, j - 1);
The package PoC.vectors can be synthesized.
Further functions are provided like:
slicing a complete row
slicing sub matrixes
flattening / serialization
creating matrix from vector / deserialization
overloaded boolean operators
row / column assignment
matrix merging
conversion to/from 1-dimensional array types containing another 1-dimensional array type
...
I am attempting to create an array of vectors in VHDL however I am getting an error in modelsim.
I have:
type read_data_array is array (0 to 73) of std_logic_vector(7 downto 0);
signal reg_data_stream : read_data_array;
I store data into the array by:
reg_data_stream(counter) <= read_data;
"read_data" is that of std_logic_vector(7 downto 0) and "counter" is a basic counter that increments from 0.
To index an array or a vector, VHDL expects an integer. If counter is a std_logic_vector, try:
to_integer(unsigned(counter)) <= read_data;
We have a type which is an array of 32 bit "std_logic_vector" of size 3, which is defined in the following way:
subtype scalar is std_logic_vector(31 downto 0);
type vector_nd is array (natural range <>) of scalar;
subtype vector_3d is vector_nd(2 downto 0);
We have a signal of type "vector_3d" which we want to multiply by 2 and put the result in a signal of type "scalar":
signal v_normal_out_sig := vector_3d;
signal mult1_in1_sig := scalar;
--...
mult1_in1_sig <= 2*signed(v_normal_out_sig(0)) when cau_state = st_cycle18;
When we compile it we get the error:
No feasible entries for infix operator "*".
What is the right way to implement what we want? We are using the following libraries:
ieee.std_logic_1164.all
ieee.std_logic_arith.all
ieee.std_logic_unsigned.all
What we did eventually is the fallowing:
mult1_in1_sig <= v_normal_out_sig(0)(31) & v_normal_out_sig(0)(29 downto 0) & '0' when cau_state = st_cycle18;
And test gave the right results for both positive and negative numbers.