I am getting this error in ModelSim 10.1c:
Fatal: (vsim-3421) Value 3079 is out of range 0 to 3078.
Fatal error in Process wr_addr at C:/videoalgo/run_chkin/veu/median/median/board/sim/../../../window_gen/rtl/fifo.vhd line 159
I have the following types and signals defined. As you see, the declared index range is only 1029 down to 0:
type memory_type is array (natural range <> ) of std_logic_vector(29 downto 0);
signal MEMORY : memory_type(1029 downto 0):= (others => (others => '0'));
signal wr_port_address :std_logic_vector(10 downto 0) := (others => '0');
signal wr_port_address_binary : std_logic_vector(10 downto 0):=(others => '0');
And the process where I'm getting the error is:
if rising_edge(Wr_Clk) then
if A_rst = '1' then
wr_port_address_binary <= (others => '0');
else
if (Wr_Ena = '1') and (fifo_full = '0') then
wr_port_address_binary <= wr_port_address_binary + 1;
-- the following is line 159
MEMORY(to_integer(unsigned(wr_port_address))) <= Wr_Data;
end if;
end if;
end if;
What process drivers the wr_port_address? You can't write to MEMORY using a number outside [0, 1029] range.
Taking the filename 'fifo.vhd' as a hint, you should reset the wr_port_address signal whenever it reaches the top of your memory. I'll assume that wr_port_address_binary is the same thing as wr_port_address apart from some weird name and/or type change (if it isn't you should really rename them).
if rising_edge(Wr_Clk) then
if A_rst = '1' then
wr_port_address <= (others => '0');
else
if (Wr_Ena = '1') and (fifo_full = '0') then
if wr_port_address < 1029 then
wr_port_address <= wr_port_address + 1;
else
wr_port_address <= (others => '0');
end if;
-- the following is line 159
MEMORY(to_integer(unsigned(wr_port_address))) <= Wr_Data;
end if;
end if;
end if;
Related
I am not very good at programming vhdl and I am running up to this error:
Error (10818): Can't infer register for "Current_Number_32[0]" at Receiver.vhd(123) because it does not hold its value outside the clock edge
Error (10818): Can't infer register for "Current_Number_32[1]" at Receiver.vhd(123) because it does not hold its value outside the clock edge
Error (10818): Can't infer register for "Current_Number_32[2]" at Receiver.vhd(123) because it does not hold its value outside the clock edge
Error (10818): Can't infer register for "Current_Number_32[3]" at Receiver.vhd(123) because it does not hold its value outside the clock edge
Error (10818): Can't infer register for "Current_Number_32[4]" at Receiver.vhd(123) because it does not hold its value outside the clock edge
Error (10818): Can't infer register for "Current_Number_32[5]" at Receiver.vhd(123) because it does not hold its value outside the clock edge
Error (10818): Can't infer register for "Current_Number_32[6]" at Receiver.vhd(123) because it does not hold its value outside the clock edge
Error (10818): Can't infer register for "Current_Number_32[7]" at Receiver.vhd(123) because it does not hold its value outside the clock edge
Error (10818): Can't infer register for "Current_Number_32[8]" at Receiver.vhd(106) because it does not hold its value outside the clock edge
Error (10818): Can't infer register for "Current_Number_32[9]" at Receiver.vhd(106) because it does not hold its value outside the clock edge
Error (10818): Can't infer register for "Current_Number_32[10]" at Receiver.vhd(106) because it does not hold its value outside the clock edge
Error (10818): Can't infer register for "Current_Number_32[11]" at Receiver.vhd(106) because it does not hold its value outside the clock edge
Error (10818): Can't infer register for "Current_Number_32[12]" at Receiver.vhd(106) because it does not hold its value outside the clock edge
Error (10818): Can't infer register for "Current_Number_32[13]" at Receiver.vhd(106) because it does not hold its value outside the clock edge
Error (10818): Can't infer register for "Current_Number_32[14]" at Receiver.vhd(106) because it does not hold its value outside the clock edge
Error (10818): Can't infer register for "Current_Number_32[15]" at Receiver.vhd(106) because it does not hold its value outside the clock edge
Error (10818): Can't infer register for "Current_Number_32[16]" at Receiver.vhd(89) because it does not hold its value outside the clock edge
Error (10818): Can't infer register for "Current_Number_32[17]" at Receiver.vhd(89) because it does not hold its value outside the clock edge
Error (10818): Can't infer register for "Current_Number_32[18]" at Receiver.vhd(89) because it does not hold its value outside the clock edge
code:
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
entity Receiver is
Port ( SYS_CLK : in STD_LOGIC;
RST : in STD_LOGIC;
DATA_ACK : out STD_LOGIC;
DATA_VALID : in STD_LOGIC;
DATA_BUS_8 : in STD_LOGIC_VECTOR (7 downto 0);
DIGIT_1 : out STD_LOGIC_VECTOR (6 downto 0);
DIGIT_2 : out STD_LOGIC_VECTOR (6 downto 0);
DIGIT_3 : out STD_LOGIC_VECTOR (6 downto 0);
DIGIT_4 : out STD_LOGIC_VECTOR (6 downto 0);
DIGIT_5 : out STD_LOGIC_VECTOR (6 downto 0);
DIGIT_6 : out STD_LOGIC_VECTOR (6 downto 0);
DIGIT_7 : out STD_LOGIC_VECTOR (6 downto 0);
DIGIT_8 : out STD_LOGIC_VECTOR (6 downto 0));
end Receiver;
architecture Behavioral of Receiver is
signal Current_Number_32 : STD_LOGIC_VECTOR (31 downto 0) := (others => '0');
function BitsToDisplay (Bits : STD_LOGIC_VECTOR (3 downto 0) := (others => '0')) return STD_LOGIC_VECTOR is
variable DisplayBits : STD_LOGIC_VECTOR (6 downto 0);
begin
case Bits is
when "0000" => DisplayBits := "1111110";
when "0001" => DisplayBits := "0110000";
when "0010" => DisplayBits := "1101110";
when "0011" => DisplayBits := "1111001";
when "0100" => DisplayBits := "0110011";
when "0101" => DisplayBits := "1011011";
when "0110" => DisplayBits := "1011111";
when "0111" => DisplayBits := "1110000";
when "1000" => DisplayBits := "1111111";
when "1001" => DisplayBits := "1111101";
when "1010" => DisplayBits := "1110111";
when "1011" => DisplayBits := "0011111";
when "1100" => DisplayBits := "1001111";
when "1101" => DisplayBits := "0111101";
when "1110" => DisplayBits := "1001111";
when "1111" => DisplayBits := "1000111";
when others => DisplayBits := "0000001";
end case;
return DisplayBits;
end function;
begin
Communication : process (SYS_CLK,RST,DATA_ACK,DATA_VALID,DATA_BUS_8)
variable Section_1 : STD_LOGIC_VECTOR (7 downto 0) := (others => '0');
variable Section_2 : STD_LOGIC_VECTOR (7 downto 0) := (others => '0');
variable Section_3 : STD_LOGIC_VECTOR (7 downto 0) := (others => '0');
variable Section_4 : STD_LOGIC_VECTOR (7 downto 0) := (others => '0');
variable Current_Section : STD_LOGIC_VECTOR (1 downto 0) := (others => '0');
variable Stage : STD_LOGIC_VECTOR (1 downto 0) := (others => '0');
begin
if (RST = '1') then
DATA_ACK <= '0';
Current_Number_32 <= (others => '0');
Section_1 := (others => '0');
Section_2 := (others => '0');
Section_3 := (others => '0');
Section_4 := (others => '0');
Current_Section := (others => '0');
Stage := (others => '0');
elsif rising_edge(SYS_CLK) then
if (Current_Section = "00") then
if (Stage = "00") and rising_edge(DATA_VALID) then
Section_1 := DATA_BUS_8;
Stage := "01";
end if;
if (Stage = "01") and (DATA_ACK = '1') then
DATA_ACK <= '0';
Stage := "00";
Current_Section := "01";
end if;
if (Stage = "01") and falling_edge(DATA_VALID) then
DATA_ACK <= '1';
end if;
end if;
if (Current_Section = "01") then
if (Stage = "00") and rising_edge(DATA_VALID) then
Section_2 := DATA_BUS_8;
Stage := "01";
end if;
if (Stage = "01") and (DATA_ACK = '1') then
DATA_ACK <= '0';
Stage := "00";
Current_Section := "10";
end if;
if (Stage = "01") and falling_edge(DATA_VALID) then
DATA_ACK <= '1';
end if;
end if;
if (Current_Section = "10") then
if (Stage = "00") and rising_edge(DATA_VALID) then
Section_3 := DATA_BUS_8;
Stage := "01";
end if;
if (Stage = "01") and (DATA_ACK = '1') then
DATA_ACK <= '0';
Stage := "00";
Current_Section := "11";
end if;
if (Stage = "01") and falling_edge(DATA_VALID) then
DATA_ACK <= '1';
end if;
end if;
if (Current_Section = "11") then
if (Stage = "00") and rising_edge(DATA_VALID) then
Section_4 := DATA_BUS_8;
Stage := "01";
end if;
if (Stage = "01") and (DATA_ACK = '1') then
Current_Number_32(31 downto 24) <= Section_1;
Current_Number_32(23 downto 16) <= Section_2;
Current_Number_32(15 downto 8) <= Section_3;
Current_Number_32(7 downto 0) <= Section_4;
DATA_ACK <= '0';
Stage := "00";
Current_Section := "00";
end if;
if (Stage = "01") and falling_edge(DATA_VALID) then
DATA_ACK <= '1';
end if;
end if;
end if;
end process Communication;
Display : process (SYS_CLK,RST,DIGIT_1,DIGIT_2,DIGIT_3,DIGIT_4,DIGIT_5,DIGIT_6,DIGIT_7,DIGIT_8)
begin
if (RST = '1') then
DIGIT_8 <= (others => '0');
DIGIT_7 <= (others => '0');
DIGIT_6 <= (others => '0');
DIGIT_5 <= (others => '0');
DIGIT_4 <= (others => '0');
DIGIT_3 <= (others => '0');
DIGIT_2 <= (others => '0');
DIGIT_1 <= (others => '0');
else
DIGIT_8 <= BitsToDisplay(Current_Number_32(3 downto 0));
DIGIT_7 <= BitsToDisplay(Current_Number_32(7 downto 4));
DIGIT_6 <= BitsToDisplay(Current_Number_32(11 downto 8));
DIGIT_5 <= BitsToDisplay(Current_Number_32(15 downto 12));
DIGIT_4 <= BitsToDisplay(Current_Number_32(19 downto 16));
DIGIT_3 <= BitsToDisplay(Current_Number_32(23 downto 20));
DIGIT_2 <= BitsToDisplay(Current_Number_32(27 downto 24));
DIGIT_1 <= BitsToDisplay(Current_Number_32(31 downto 28));
end if;
end process Display;
end Behavioral;
Can anyone please explain what I am doing wrong here?
I have added this code as a block to a block diagram with two other codes but before I did that compiling revealed no errors.
This code does not need to run on an actual fpga because this is a school assignment so I only need to simulate it. does that remove this error?
Trim your sensitivity list down to this:
process (SYS_CLK,RST)
You don't want to execute the process when input data changes. Only when the clock or reset changes.
Here is the code:
process(SRSTN, CSN, WRN,AB) is
begin
if SRSTN = '0' then
WR0 <= (OTHERS => '0');
elsif CSN = '0' then
if WRN = '0' then
case AB(15 downto 0) is
when "0101000100010000" =>
WR0(15 downto 0) <= DB(15 downto 0);
when OTHERS => NULL;
WR0(15 downto 8) <= "00000000" ;
end case;
end if;
end if;
end process;
I'm wondering when will
WR0(15 downto 8) <= "00000000"be executed. Is it assigned everytime except AB equals 0101000100010000?
You have to use signal or variable (inside the process). A possible solution could be:
architecture Beh of Test is
signal temp : std_logic_vector((WR0'LENGTH - 1) downto 0) := (others => '0');
begin
WR0 <= std_logic_vector(temp);
process(SRSTN, CSN, WRN,AB) is
begin
if SRSTN = '0' then
temp <= (OTHERS => '0');
elsif CSN = '0' then
if WRN = '0' then
case AB(15 downto 0) is
when "0101000100010000" =>
temp(15 downto 0) <= DB(15 downto 0);
when OTHERS =>
temp(15 downto 8) <= "00000000" ;
end case;
end if;
end if;
end process;
end Beh;
The WR0 output will be imediatly assigned if one of the inputs SRSTN, CSN, WRN, AB is changing.
I wrote a simple Real Time Clock code. However in simulation it shows X instead of output bits, also a glitch after value "000001" in Seconds output.
Waveform Picture.
Could you please advise what is wrong with the code?
VHDL Code
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_unsigned.ALL; -- Enables Adding
entity rtc_timer is
generic( CLK_FREQ : integer := 10);
port
(
nRST : in std_logic;
clk : in std_logic;
Seconds : inout std_logic_vector(5 downto 0);
Minutes : inout std_logic_vector(5 downto 0);
Hours : inout std_logic_vector(4 downto 0)
);
end rtc_timer;
architecture Behavioral of rtc_timer is
signal counter : integer;
begin
process(nRST, clk)
begin
if rising_edge(clk) then
-- Negative Reset Signal
if nRST = '0' then
counter <= 0;
Seconds <= (others => '0');
Minutes <= (others => '0');
Hours <= (others => '0');
elsif counter = CLK_FREQ - 1 then
counter <= 0;
if Seconds = 59 then
Seconds <= (others => '0');
if Minutes = 59 then
Minutes <= (others => '0');
if Hours = 23 then
Hours <= (others => '0');
else Hours <= Hours + 1;
end if;
else Minutes <= Minutes + 1;
end if;
else Seconds <= Seconds + 1;
end if;
else counter <= counter + 1;
end if;
end if;
end process;
end Behavioral;
Error (10395): VHDL Conditional Signal Assignment error at vga.vhd(146): conditional waveforms must have same number of elements.
in this line show me error
R<=intensity WHEN red_switch='0' AND dena='1' ELSE (OTHERS=>'1');
I really don't know what's wrong vhdl Altera code error but it didn't solve my problem. thanks in advance.
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_arith.all;
LIBRARY lpm;
USE lpm.lpm_components.all;
----------------------------------------------------------
ENTITY vga IS
GENERIC (
Ha: INTEGER := 96; --Hpulse
Hb: INTEGER := 144; --Hpulse+HBP
Hc: INTEGER := 784; --Hpulse+HBP+Hactive
Hd: INTEGER := 800; --Hpulse+HBP+Hactive+HFP
Va: INTEGER := 2; --Vpulse
Vb: INTEGER := 35; --Vpulse+VBP
Vc: INTEGER := 515; --Vpulse+VBP+Vactive
Vd: INTEGER := 525); --Vpulse+VBP+Vactive+VFP
PORT (
clk: IN STD_LOGIC; --50MHz in our board
red_switch, green_switch, blue_switch: IN STD_LOGIC;
pixel_clk: BUFFER STD_LOGIC;
Hsync, Vsync: BUFFER STD_LOGIC;
R, G, B: OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
nblanck, nsync : OUT STD_LOGIC);
END vga;
----------------------------------------------------------
ARCHITECTURE vga OF vga IS
SIGNAL Hactive, Vactive, dena: STD_LOGIC;
SIGNAL address: STD_LOGIC_VECTOR(8 DOWNTO 0);
SIGNAL intensity: STD_LOGIC_VECTOR(9 DOWNTO 0);
BEGIN
-------------------------------------------------------
--Part 1: CONTROL GENERATOR
-------------------------------------------------------
--Static signals for DACs:
nblanck <= '1'; --no direct blanking
nsync <= '0'; --no sync on green
--Create pixel clock (50MHz->25MHz):
PROCESS (clk)
BEGIN
IF (clk'EVENT AND clk='1') THEN
pixel_clk <= NOT pixel_clk;
END IF;
END PROCESS;
--Horizontal signals generation:
PROCESS (pixel_clk)
VARIABLE Hcount: INTEGER RANGE 0 TO Hd;
BEGIN
IF (pixel_clk'EVENT AND pixel_clk='1') THEN
Hcount := Hcount + 1;
IF (Hcount=Ha) THEN
Hsync <= '1';
ELSIF (Hcount=Hb) THEN
Hactive <= '1';
ELSIF (Hcount=Hc) THEN
Hactive <= '0';
ELSIF (Hcount=Hd) THEN
Hsync <= '0';
Hcount := 0;
END IF;
END IF;
END PROCESS;
--Vertical signals generation:
PROCESS (Hsync)
VARIABLE Vcount: INTEGER RANGE 0 TO Vd;
BEGIN
IF (Hsync'EVENT AND Hsync='0') THEN
Vcount := Vcount + 1;
IF (Vcount=Va) THEN
Vsync <= '1';
ELSIF (Vcount=Vb) THEN
Vactive <= '1';
ELSIF (Vcount=Vc) THEN
Vactive <= '0';
ELSIF (Vcount=Vd) THEN
Vsync <= '0';
Vcount := 0;
END IF;
END IF;
END PROCESS;
---Display enable generation:
dena <= Hactive AND Vactive;
-------------------------------------------------------
--Part 2: IMAGE GENERATOR
-------------------------------------------------------
PROCESS (Hsync, Vsync, Vactive, dena, red_switch,
green_switch, blue_switch)
VARIABLE line_counter: INTEGER RANGE 0 TO Vc;
BEGIN
IF (Vsync='0') THEN
line_counter := 0;
ELSIF (Hsync'EVENT AND Hsync='1') THEN
IF (Vactive='1') THEN
line_counter := line_counter + 1;
END IF;
END IF;
IF (dena='1') THEN
IF (line_counter=1) THEN
R <= (OTHERS => '1');
G <= (OTHERS => '0');
B <= (OTHERS => '0');
ELSIF (line_counter>1 AND line_counter<=3) THEN
R <= (OTHERS => '0');
G <= (OTHERS => '1');
B <= (OTHERS => '0');
ELSIF (line_counter>3 AND line_counter<=6) THEN
R <= (OTHERS => '0');
G <= (OTHERS => '0');
B <= (OTHERS => '1');
ELSE
R <= (OTHERS => red_switch);
G <= (OTHERS => green_switch);
B <= (OTHERS => blue_switch);
END IF;
ELSE
R <= (OTHERS => '0');
G <= (OTHERS => '0');
B <= (OTHERS => '0');
END IF;
END PROCESS;
--END vga;
-------------------------------------------
--ROM instantiation:
myrom: lpm_rom
GENERIC MAP (
lpm_widthad => 9, --address width
lpm_outdata => "UNREGISTERED",
lpm_address_control => "REGISTERED",
lpm_file => "pic_6.mif", --data file
lpm_width => 10) --data width
PORT MAP (
inclock=>NOT pixel_clk, address=>address, q=>intensity);
--Create address (row number):
PROCESS (Vsync, Hsync)
VARIABLE line_counter: INTEGER RANGE 0 TO Vd;
BEGIN
IF (Vsync='0') THEN
line_counter := 0;
ELSIF (Hsync'EVENT AND Hsync='1') THEN
IF (Vactive='1') THEN
line_counter := line_counter + 1;
END IF;
END IF;
address <= conv_std_logic_vector(line_counter, 9);
END PROCESS;
-- --Assign color values to R/G/B:
R<=intensity WHEN red_switch='0' AND dena='1' ELSE (OTHERS=>'1');
G<=intensity WHEN green_switch='0' AND dena='1' ELSE (OTHERS=>'1');
B<=intensity WHEN blue_switch='0' AND dena='1' ELSE (OTHERS=>'1');
END vga;
Signal R is 8 bits wide:
R, G, B: OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
while signal intensity is 10 bits wide:
SIGNAL intensity: STD_LOGIC_VECTOR(9 DOWNTO 0);
This is not allowed in VHDL. Both must be the same width; you must either explicitly truncate intensity or extend R.
As part of adaptations to an existing large design on Artix-7 FPGA, I implemented a simple counting mechanism, something similar to "Archticture with 'constant' ", so that in the future, I can just change the value of the constant and not worry too much about where it is used.
However, it led to several timing failures and I went back to the normal way to increment a counter, by adding a 1, which resolved the timing failures. Here are the entity and the 2 architectures that I tried synthesizing in Vivado 2016.4 tool. But the Project Summary tab in Vivado shows no resources except IO was used.! So my question is, does declaring constants in VHDL result in more hardware than usual? What is the difference between the 2 implementations?
Entity
entity counter is
Port(
i_clk : in std_logic;
i_rst : in std_logic;
o_cnt : out std_logic_vector(7 downto 0)
);
end counter;
Architecture with 'constant'
architecture Behavioral of counter is
signal s_cnt : unsigned(7 downto 0) := (others => '0');
signal s_max : unsigned(7 downto 0) := (others => '1');
constant c_INCR : unsigned(3 downto 0) := x"1";
begin
process (i_clk) begin
if rising_edge(i_clk) then
if i_rst = '1' then
s_cnt <= (others => '0');
else
o_cnt <= std_logic_vector(s_cnt);
if s_cnt = s_max then
s_cnt <= (others => '0');
else
s_cnt <= s_cnt + c_INCR;
end if;
end if;
end if;
end process;
end Behavioral;
Architecture with '+1'
architecture Behavioral of counter is
signal s_cnt : unsigned(7 downto 0) := (others => '0');
signal s_max : unsigned(7 downto 0) := (others => '1');
begin
process (i_clk) begin
if rising_edge(i_clk) then
if i_rst = '1' then
s_cnt <= (others => '0');
else
o_cnt <= std_logic_vector(s_cnt);
if s_cnt = s_max then
s_cnt <= (others => '0');
else
s_cnt <= s_cnt + 1;
end if;
end if;
end if;
end process;
end Behavioral;