Here is the code:
process(SRSTN, CSN, WRN,AB) is
begin
if SRSTN = '0' then
WR0 <= (OTHERS => '0');
elsif CSN = '0' then
if WRN = '0' then
case AB(15 downto 0) is
when "0101000100010000" =>
WR0(15 downto 0) <= DB(15 downto 0);
when OTHERS => NULL;
WR0(15 downto 8) <= "00000000" ;
end case;
end if;
end if;
end process;
I'm wondering when will
WR0(15 downto 8) <= "00000000"be executed. Is it assigned everytime except AB equals 0101000100010000?
You have to use signal or variable (inside the process). A possible solution could be:
architecture Beh of Test is
signal temp : std_logic_vector((WR0'LENGTH - 1) downto 0) := (others => '0');
begin
WR0 <= std_logic_vector(temp);
process(SRSTN, CSN, WRN,AB) is
begin
if SRSTN = '0' then
temp <= (OTHERS => '0');
elsif CSN = '0' then
if WRN = '0' then
case AB(15 downto 0) is
when "0101000100010000" =>
temp(15 downto 0) <= DB(15 downto 0);
when OTHERS =>
temp(15 downto 8) <= "00000000" ;
end case;
end if;
end if;
end process;
end Beh;
The WR0 output will be imediatly assigned if one of the inputs SRSTN, CSN, WRN, AB is changing.
Related
I am getting this error in ModelSim 10.1c:
Fatal: (vsim-3421) Value 3079 is out of range 0 to 3078.
Fatal error in Process wr_addr at C:/videoalgo/run_chkin/veu/median/median/board/sim/../../../window_gen/rtl/fifo.vhd line 159
I have the following types and signals defined. As you see, the declared index range is only 1029 down to 0:
type memory_type is array (natural range <> ) of std_logic_vector(29 downto 0);
signal MEMORY : memory_type(1029 downto 0):= (others => (others => '0'));
signal wr_port_address :std_logic_vector(10 downto 0) := (others => '0');
signal wr_port_address_binary : std_logic_vector(10 downto 0):=(others => '0');
And the process where I'm getting the error is:
if rising_edge(Wr_Clk) then
if A_rst = '1' then
wr_port_address_binary <= (others => '0');
else
if (Wr_Ena = '1') and (fifo_full = '0') then
wr_port_address_binary <= wr_port_address_binary + 1;
-- the following is line 159
MEMORY(to_integer(unsigned(wr_port_address))) <= Wr_Data;
end if;
end if;
end if;
What process drivers the wr_port_address? You can't write to MEMORY using a number outside [0, 1029] range.
Taking the filename 'fifo.vhd' as a hint, you should reset the wr_port_address signal whenever it reaches the top of your memory. I'll assume that wr_port_address_binary is the same thing as wr_port_address apart from some weird name and/or type change (if it isn't you should really rename them).
if rising_edge(Wr_Clk) then
if A_rst = '1' then
wr_port_address <= (others => '0');
else
if (Wr_Ena = '1') and (fifo_full = '0') then
if wr_port_address < 1029 then
wr_port_address <= wr_port_address + 1;
else
wr_port_address <= (others => '0');
end if;
-- the following is line 159
MEMORY(to_integer(unsigned(wr_port_address))) <= Wr_Data;
end if;
end if;
end if;
I build a 4 bit sequence detector with a 16-bit input.
I wanna now how often the sequence appears in the 16 bits.
For that I use this code:
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
ENTITY seqdec IS
PORT ( X: IN std_logic_vector(15 DOWNTO 0);
CLK: IN std_logic;
RESET:IN std_logic;
LOAD: IN std_logic;
Y: OUT std_logic);
END seqdec;
ARCHITECTURE SEQ OF seqdec IS
TYPE statetype IS (s0, s1, s2, s3, s4);
SIGNAL state, next_state: statetype;
SIGNAL counter: std_logic_vector(3 DOWNTO 0) :="0000" ;
SIGNAL temp: std_logic_vector(15 DOWNTO 0);
SIGNAL so: std_logic;
BEGIN
STATE_AKT: PROCESS (CLK, RESET)
BEGIN
IF RESET = '1' THEN
state <= s0 ;
counter <= (OTHERS => '0') ;
ELSIF CLK = '1' AND CLK'event THEN
state <= next_state ;
END IF;
END PROCESS STATE_AKT;
PISO: PROCESS (CLK, LOAD, X)
BEGIN
IF (LOAD = '1') THEN
temp(15 DOWNTO 0) <= X(15 DOWNTO 0);
ELSIF (CLK'event and CLK='1') THEN
so <= temp(15) ;
temp(15 DOWNTO 1) <= temp(14 DOWNTO 0);
temp(0) <= '0';
END IF;
END PROCESS PISO;
STATE_CAL: PROCESS (so,state)
BEGIN
CASE state IS
WHEN s0 => IF so = '0' THEN next_state <= s0 ;
ELSE next_state <= s1 ;
END IF;
WHEN s1 => IF so = '0' THEN next_state <= s1;
ELSE next_state <= s2 ;
END IF;
WHEN s2 => IF so = '0' THEN next_state <= s3 ;
ELSE next_state <= s2 ;
END IF;
WHEN s3 => IF so = '0' THEN next_state <= s0 ;
ELSE next_state <= s4 ;
END IF;
WHEN s4 => IF so = '0' THEN next_state <= s0;
ELSE next_state <= s2 ;
END IF;
WHEN OTHERS => NULL;
END CASE;
END PROCESS STATE_CAL;
STATE_Y: PROCESS (state)
BEGIN
CASE state IS
WHEN s4 =>
Y <= '1';
counter <= counter + '1';
WHEN OTHERS => Y <= '0' ;
END CASE;
END PROCESS STATE_Y;
END SEQ;
But neither my counter reset nor my incrementation of counter is working.
The rest is working perfect and fine.
Has somebody a hint or an idea for me?
The programm is now working fine in ModelSim, but I struggle with getting it on the board.
I simulated it several times in ModelSim, with different parameters and it works fine, so the functional part is fine.
My code looks now this way:
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
ENTITY seqdec IS
PORT ( X: IN std_logic_vector(15 DOWNTO 0);
CLK: IN std_logic;
RESET: IN std_logic;
LOAD: IN std_logic;
DIGIT: OUT std_logic_vector(6 DOWNTO 0) := "1111110";
COUT: OUT std_logic_vector(2 DOWNTO 0);
Y: OUT std_logic);
END seqdec;
ARCHITECTURE SEQ OF seqdec IS
TYPE statetype IS (s0, s1, s2, s3, s4);
SIGNAL state: statetype;
SIGNAL next_state: statetype:=s0;
SIGNAL counter: std_logic_vector(2 DOWNTO 0) :="000" ;
SIGNAL temp: std_logic_vector(15 DOWNTO 0);
SIGNAL so: std_logic := 'U';
-------------------Aktualisierung des Zustandes--------------------------------
BEGIN
STATE_AKT: PROCESS (CLK, RESET)
BEGIN
IF RESET = '1' THEN
state <= s0;
ELSIF CLK = '1' AND CLK'event THEN
state <= next_state ;
END IF;
END PROCESS STATE_AKT;
---------------------Counter---------------------------------------------------
COUNT: PROCESS (state, RESET)
BEGIN
IF (RESET = '1') THEN
counter <= (OTHERS => '0');
ELSIF (state = s4) THEN
counter <= counter + '1';
COUT <= counter;
END IF;
END PROCESS COUNT;
-------------------PiSo für die Eingabe des zu Prüfenden Vektors---------------
PISO: PROCESS (CLK, LOAD, X)
BEGIN
IF (LOAD = '1') THEN
temp(15 DOWNTO 0) <= X(15 DOWNTO 0);
ELSIF (CLK'event and CLK='1') THEN
so <= temp(15);
temp(15 DOWNTO 1) <= temp(14 DOWNTO 0);
temp(0) <= '0';
END IF;
END PROCESS PISO;
-------------------Zustandsabfrage und Berechnung------------------------------
STATE_CAL: PROCESS (so,state)
BEGIN
CASE state IS
WHEN s0 => IF so = '0' THEN next_state <= s0 ;
ELSIF (so = '1') THEN next_state <= s1 ;
END IF;
WHEN s1 => IF so = '0' THEN next_state <= s1;
ELSIF (so = '1') THEN next_state <= s2 ;
END IF;
WHEN s2 => IF so = '0' THEN next_state <= s3 ;
ELSIF (so = '1') THEN next_state <= s2 ;
END IF;
WHEN s3 => IF so = '0' THEN next_state <= s0 ;
ELSIF (so = '1') THEN next_state <= s4 ;
END IF;
WHEN s4 => IF so = '0' THEN next_state <= s0;
ELSIF (so = '1') THEN next_state <= s2 ;
END IF;
WHEN OTHERS => NULL;
END CASE;
END PROCESS STATE_CAL;
-------------------Ausgang-----------------------------------------------------
STATE_Y: PROCESS (state)
BEGIN
CASE state IS
WHEN s4 =>
Y <= '1';
WHEN OTHERS => Y <= '0' ;
END CASE;
END PROCESS STATE_Y;
-------------------7 Segment---------------------------------------------------
SEVEN_SEG: PROCESS (counter, CLK)
BEGIN
IF (RESET = '1') THEN
DIGIT <= "1111110";
END IF;
CASE counter IS
WHEN "000" => DIGIT <= "1111110";
WHEN "001" => DIGIT <= "0110000";
WHEN "010" => DIGIT <= "1101101";
WHEN "011" => DIGIT <= "1111001";
WHEN "100" => DIGIT <= "0110011";
WHEN "101" => DIGIT <= "1011011";
WHEN OTHERS => NULL;
END CASE;
END PROCESS SEVEN_SEG;
END SEQ;
When i put it on the board the 7-segment will show a "3".
I would assume, as the functional part seems to be good,that it has to do somethink with the timings, but i can't find any solution to it. If some experience VHDL-programmer could give me a new hint that would be great.
Best regards
Adrian
entity hex_kp is
Port ( row : out STD_LOGIC_VECTOR (3 downto 0);
coloumn : in STD_LOGIC_VECTOR (3 downto 0);
sevenseg : out STD_LOGIC_VECTOR (7 downto 0);
ca : out STD_LOGIC_VECTOR (3 downto 0));
end hex_kp;
architecture Behavioral of hex_kp is
begin
ca <="0111";
if(row = "0111") then
if(coloumn = "0111") then sevenseg <= "00000110" ;
elsif (coloumn = "1011") then sevenseg <= "01011011" ;
elsif (coloumn = "1101") then sevenseg <= "01001111" ;
elsif (coloumn = "1110") then sevenseg <= "01110001" ;
end if;
end if;
This my part of my vhdl code for 4x4 keypad scanner for Basys2. It gives an error to "if(row = "0111") then" statement. I couldn't find why help please.
You can use a conditional signal assignment statement:
architecture behave of hex_kp is
begin
ca <="0111";
-- if(row = "0111") then
--
-- if(coloumn = "0111") then sevenseg <= "00000110" ;
-- elsif (coloumn = "1011") then sevenseg <= "01011011" ;
-- elsif (coloumn = "1101") then sevenseg <= "01001111" ;
-- elsif (coloumn = "1110") then sevenseg <= "01110001" ;
-- end if;
-- end if;
sevenseg <= "00000110" when coloumn = "0111" and row = "0111" else
"01011011" when coloumn = "1011" and row = "0111" else
"01001111" when coloumn = "1101" and row = "0111" else
"01110001" when coloumn = "1110" and row = "0111" else
"00000000" when row = "0111";
end architecture behave;
Note that like your Stack Exchange question (vhdl code interfacing keypad with fpga) There are inferred latches on sevenseg caused by using row = "0111" as a condition for assignment.
The above architecture gives the same result as my answer on your Stack Exchange question (vhdl code interfacing keypad with fpga).
Your modified code analyzes, elaborates and the added testbench there simulates the above architecture:
Getting rid of the latches would be as simple as removing the row = "0111" from the final choice in the conditional signal assignment above, or in the the Stack Exchange example using a case statement, providing an else for the enclosing if statement.
The entire code including the testbench and both architectures, predicated on using row as an input:
library ieee;
use ieee.std_logic_1164.all;
entity hex_kp is
port (
row: in std_logic_vector (3 downto 0);
coloumn: in std_logic_vector (3 downto 0); -- 'column 'is mispelled
sevenseg: out std_logic_vector (7 downto 0); -- why is 7 segs 8 long?
ca : out std_logic_vector (3 downto 0)
);
end entity hex_kp;
architecture behavioral of hex_kp is
-- signal row: std_logic_vector(3 downto 0); -- who drive row?
begin -- this was missing
UNLABELLED:
process(row, coloumn) -- was 'column' (didn't match declaration)
begin
ca <="0111";
if row = "0111" then
case coloumn is
when "0111" =>
sevenseg <= "00000110";
when "1011" =>
sevenseg <= "01011011";
when "1101" =>
sevenseg <= "01001111";
when "1110" =>
sevenseg <= "01110001";
when others =>
sevenseg <= (others => '0');
end case;
end if;
end process;
end architecture behavioral;
architecture behave of hex_kp is
begin
ca <="0111";
-- if(row = "0111") then
--
-- if(coloumn = "0111") then sevenseg <= "00000110" ;
-- elsif (coloumn = "1011") then sevenseg <= "01011011" ;
-- elsif (coloumn = "1101") then sevenseg <= "01001111" ;
-- elsif (coloumn = "1110") then sevenseg <= "01110001" ;
-- end if;
-- end if;
sevenseg <= "00000110" when coloumn = "0111" and row = "0111" else
"01011011" when coloumn = "1011" and row = "0111" else
"01001111" when coloumn = "1101" and row = "0111" else
"01110001" when coloumn = "1110" and row = "0111" else
"00000000" when row = "0111";
end architecture behave;
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity hex_kp_tb is
end entity;
architecture foo of hex_kp_tb is
signal row: std_logic_vector (3 downto 0);
signal coloumn: std_logic_vector (3 downto 0);
signal sevenseg: std_logic_vector (7 downto 0);
signal ca: std_logic_vector (3 downto 0);
signal count: unsigned (7 downto 0) := (others => '0');
begin
DUT:
entity work.hex_kp
port map (
row => row,
coloumn => coloumn,
sevenseg => sevenseg,
ca => ca
);
STIMULUS:
process
begin
row <= std_logic_vector (count(3 downto 0));
coloumn <= std_logic_vector (count(7 downto 4));
wait for 100 ns;
count <= count + 1;
if count = "11111111" then
wait;
end if;
end process;
end architecture;
You are trying to use an if statement in a concurrent context. However, if statements need to be within a sequential context - for instance a process statement:
process(row, column)
begin
if(row = "0111") then
if(coloumn = "0111") then
sevenseg <= "00000110";
elsif(coloumn = "1011") then
sevenseg <= "01011011";
elsif(coloumn = "1101") then
sevenseg <= "01001111";
elsif(coloumn = "1110") then
sevenseg <= "01110001";
end if;
end if;
end process;
However - note that if you synthesize the above, it will most probably end up giving you a nice set of latches (which you usually don't want), since you are not assigning sevenseg in all possible cases (if row is different from 0111, or if coloumn doesn't match any of the if statements).
To fix it, either 1) use a clocked process, or 2) assign sevenseg to a default value if row and coloumn do not match one of the specified cases. For instance:
process(row, column)
begin
sevenseg <= (others => '0');
if(row = "0111") then
if(coloumn = "0111") then
sevenseg <= "00000110";
elsif(coloumn = "1011") then
sevenseg <= "01011011";
elsif(coloumn = "1101") then
sevenseg <= "01001111";
elsif(coloumn = "1110") then
sevenseg <= "01110001";
end if;
end if;
end process;
I've added the sevenseg <= (others => '0'); which will make sevenseg default to all 0's, if none of the specified cases are hit - if they are, they will override the added line, and set sevenseg to the appropriate value.
An even nicer way to do it is to use a case statement, since that probably better describes what you actually want:
process(row, column)
begin
if(row = "0111") then
case coloumn is
when "0111" =>
sevenseg <= "00000110";
when "1011" =>
sevenseg <= "01011011";
when "1101" =>
sevenseg <= "01001111";
when "1110" =>
sevenseg <= "01110001";
when others =>
sevenseg <= (others => '0');
end case;
else
sevenseg <= (others => '0');
end if;
end process;
I'm fairly new to vhdl, but I'm trying to build a snake game. In the loop below the constraint of eating='1' and ate='0' doesn't seem to work. It's as if the code nested within that if statement is always ran.
The if statement in question
if(snake_body_ram(i)(14)='1' or (eating='1' and ate='0'))then
Here's the entire process
process(move, direction, snake_head_reg, snake_body_ram, clk, head_coord, direction, eating)
variable dir_next, tail_next_dir : std_logic_vector(1 downto 0);
variable coord_next : std_logic_vector(13 downto 0);
variable ate: std_logic := '0';
variable value : unsigned(5 downto 0) := (others=>'0');
begin
if(clk'event and clk='1')then
if(move='1')then
dir_next := snake_head_reg(16 downto 15);
coord_next := snake_head_reg(13 downto 0);
snake_head_reg(16 downto 15) <= direction;
snake_head_reg(13 downto 0) <= head_coord;
ate:='0';
--look here brian
bodyLabel:
for i in 0 to 35 loop
if(snake_body_ram(i)(14)='1' or (eating='1' and ate='0'))then
snake_body_ram(i)(16 downto 15) <= dir_next;
snake_body_ram(i)(13 downto 0) <= coord_next;
snake_body_ram(i)(14) <= '1';
if(eating='1')then
ate:='1';
end if;
dir_next := snake_body_ram(i)(16 downto 15);
coord_next := snake_body_ram(i)(13 downto 0);
if(i > 1)then
tail_next_dir:=snake_body_ram(i-1)(16 downto 15);
end if;
end if;
end loop;
snake_tail_reg(13 downto 0) <= coord_next;
snake_tail_reg(14)<='1';
snake_tail_reg(16 downto 15) <= tail_next_dir;
end if;
end if;
end process;
Here's the process that sets "eating"
process(food_reg, snake_head_reg, clk, move, state, btn, snake_tail_reg, snake_body_ram)
--variable ate : std_logic := '0';
begin
--if(clk'event and clk='1' and move='1' and state=play)then
if(clk'event and clk='1')then
eating <= '0';
if(move='1' and state=play)then
you_lose <= '0';
--if()then
if(food_reg = snake_head_reg(13 downto 0))then
--ate food
food_eaten <= food_eaten_next;
eating <= '1';
elsif(snake_head_reg(13 downto 0) = snake_tail_reg(13 downto 0))then
--hit tail
you_lose <= '1';
elsif(unsigned(snake_head_reg(13 downto 7)) < 2 or unsigned(snake_head_reg(13 downto 7)) > 77 or unsigned(snake_head_reg(6 downto 0)) < 2 or unsigned(snake_head_reg(6 downto 0)) > 57)then
--hit a wall
you_lose <= '1';
else
--check for body
bodyLabel:
for i in 0 to 35 loop
if(snake_body_ram(i)(14)='1' and you_lose = '0')then
if(snake_head_reg(13 downto 0) = snake_body_ram(i)(13 downto 0)) then
you_lose <= '1';
exit;
end if;
else
exit;
end if;
end loop;
end if;
--end if;
end if;
else
end if;
end process;
I've tried to include the information necessary short of sharing the entire file. If you need more information please let me know. Thanks for even taking the time to read through this.
I want to make a FSM model of FIR, for that I need to write FIR calculation code line in FSM implementation.
Here is the actual and correct code for FIR
entity fir_4tap is
port( Clk : in std_logic; --clock signal
Clk_fast : in std_logic;
-- Xin : in signed(7 downto 0); --input signal
bit_in : in std_logic;
bit_out : out std_logic;
Yout : out signed(15 downto 0) --filter output
);
end fir_4tap;
architecture Behavioral of fir_4tap is
signal add_out3 : signed(15 downto 0) := (others => '0');
signal index : unsigned(2 downto 0) := (others =>'0');
signal counter : unsigned(3 downto 0) := (others => '0');
signal p : unsigned(1 downto 0) := (others => '0');
signal k : unsigned(1 downto 0) := (others => '0');
signal j : unsigned(1 downto 0) := (others => '0');
type array_signed is array(8 downto 0) of signed(7 downto 0);
signal z : array_signed := (others => "00000000");
type array_signed1 is array(3 downto 0) of signed(7 downto 0);
signal H : array_signed1 := (others => "00000000");
signal Xin : array_signed1 := (others => "00000000");
begin
z(0) <= to_signed(-3,8);
z(1) <= to_signed(1,8);
z(2) <= to_signed(0,8);
z(3) <= to_signed(-2,8);
z(4) <= to_signed(-1,8);
z(5) <= to_signed(4,8);
z(6) <= to_signed(-5,8);
z(7) <= to_signed(6,8);
z(8) <= to_signed(0,8);
H(0) <= to_signed(-2,8);
H(1) <= to_signed(-1,8);
H(2) <= to_signed(3,8);
H(3) <= to_signed(4,8);
process (clk)
begin
if (rising_edge(Clk)) then
index <= index +1;
if (index = "111") then
Xin(to_integer(p)) <= z(to_integer(counter)); k <= p;
p <= p + 1;
***-- This part of the code has problem, I want to write the line which is summing --up for add_out3 in a for loop.***
add_out3 <= (others => '0');
add_out3 <= Xin(to_integer(k))*H(to_integer(j)) + Xin(to_integer(k-1))*H(to_integer(j+1)) + Xin(to_integer(k-2))*H(to_integer(j+2)) + Xin(to_integer(k-3))*H(to_integer(j+3));
Yout <= add_out3;
end if;
end if;
end process;
end Behavioral;
Now Below is the FSM implementation try by me but not getting the same out sample as input can somebody tell me what could be the problem in the code?
----------------FSM implementation of the FIR filter ----------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
entity test is
port( Clk : in std_logic; --clock signal
Clk_fast : in std_logic;
bit_in : in std_logic;
bit_out : out std_logic;
Yout : out signed(15 downto 0) --filter output
);
end test;
architecture Behavioral of test is
signal data_buffer : signed(7 downto 0) := (others => '0');
signal index : unsigned(2 downto 0) := (others =>'0');
signal counter : unsigned(3 downto 0) := (others => '0');
type array_signed is array(8 downto 0) of signed(7 downto 0);
signal z : array_signed := (others => "00000000");
type array_signed1 is array(3 downto 0) of signed(7 downto 0);
signal H : array_signed1 := (others => "00000000");
signal input : signed(7 downto 0) := (others => '0');
type MULT_TYPE is array(3 downto 0) of signed(15 downto 0);
signal MULT_array : MULT_TYPE := (others => "0000000000000000");
type ADD_TYPE is array(3 downto 0) of signed(15 downto 0);
signal ADD_array : ADD_TYPE := (others => "0000000000000000");
constant ZERO : signed(15 downto 0) := (others => '0');
type state_type is (s0,s1,s2,s3); --type of state machine.
signal current_s : state_type := s0; --current and next state declaration.
signal next_s : state_type := s0;
signal reset : std_logic := '0';
signal go : std_logic := '0';
signal change_state : std_logic := '0' ;
signal counter_FSM_monitor : unsigned( 6 downto 0) := "0000000";
begin
z(0) <= to_signed(-3,8);
z(1) <= to_signed(1,8);
z(2) <= to_signed(0,8);
z(3) <= to_signed(-2,8);
z(4) <= to_signed(-1,8);
z(5) <= to_signed(4,8);
z(6) <= to_signed(-5,8);
z(7) <= to_signed(6,8);
z(8) <= to_signed(0,8);
H(0) <= to_signed(-2,8);
H(1) <= to_signed(-1,8);
H(2) <= to_signed(3,8);
H(3) <= to_signed(4,8);
process (Clk) is
begin
if falling_edge(Clk) then
data_buffer(to_integer(index)) <= bit_in;
index <= index +1;
if (index = "111") then
input <= z(to_integer(counter));
counter <= counter + 1;
if(counter = "1000") then
counter <= "0000";
end if;
end if;
end if;
end process;
process (clk_fast)
begin
if (falling_edge(clk_fast)) then
counter_FSM_monitor <= counter_FSM_monitor + 1;
if( to_integer(counter_FSM_monitor) = 76) then
counter_FSM_monitor <= "0000000";
end if;
case change_state is
when '1' =>
current_s <= next_s; --state change.
when '0' => --current_s <= s0;
when others =>
end case;
end if;
end process;
Process(current_s,input)
begin
if ( to_integer(counter_FSM_monitor) < 64 ) then
-- waiting for the Input
elsif (to_integer(counter_FSM_monitor) >= 64 and to_integer(counter_FSM_monitor) < 76) then
---------------------------------------------- FSM ----------------------------------------
case current_s is
when s0 =>
mult_array(0) <= input*H(3);
ADD_array(0) <= ZERO + mult_array(0);
next_s <= s1;
change_state <= '1';
when s1 =>
mult_array(1) <= input*H(2);
ADD_array(1) <= mult_array(1) + ADD_array(0);
next_s <= s2;
change_state <= '1';
when s2 =>
mult_array(2) <= input*H(1);
ADD_array(2) <= mult_array(2) + ADD_array(1);
next_s <= s3;
change_state <= '1';
when s3 =>
mult_array(3) <= input*H(0);
ADD_array(3) <= mult_array(3) + ADD_array(2);
Yout <= ADD_array(3);
next_s <= s0;
change_state <= '1';
when others =>
next_s <= s0;-- never comes here
change_state <= '1';
end case;
---------------------------------------------- FSM ----------------------------------------
end if;
end process;
end Behavioral;
How ever I am not able to receive the same output which I received by the first code.
FSM code gives the correct output for the first out but from the second out sample it gives wrong result.Can somebody tell me what I am doing wrong ?
This answer is for the initial version of the question but Now question has been changed.
Made add_out3 a variable instead of a signal.
for i in 0 to 3 loop
add_out3 := add_out3 + Xin(k-i)*H(i);
end loop;
Did the above changes in the for loop It works fine.
So the code in my question is a correct code for FIR also, works smoothly.
Learnt that one needs to be very careful while using signal or variables. All the signals get a new value at the same time i.e at the end of clock period, while in variables values gets updated as assigned within a process. Tried to run the simulation step by step and figured out the problem.