VHDL FSM with a counter inside - vhdl

Question

I am new here and here is my question:
I have a state machine with 3 states(s0,s1.s2) and input:(reset, clk, start) and output (done). My state machine works like this: on reset it comes to s0, and then if start = '1' goes to s2 and in this state I want it to stay there for 12 clock cycles (12 clock cycle delay) and then goes to s2 and done ='1' here and then back to s0.
My codes goes like this :
My code seems fine but my simulation result is not ok.
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
ENTITY fsm_count IS
port(clk : in std_logic;
reset : in std_logic;
start : in std_logic ;
don : out std_logic );
END ENTITY fsm_count;
--
ARCHITECTURE arc OF fsm_count IS
type statetype is (s0,s1,s2);
signal pr_state,nx_state : statetype;
signal s_counter : std_logic_vector (3 downto 0):=(others=>'0'); -- zero
begin
fsmcount: process(clk,reset,pr_state,start)
begin
if reset = '1'then pr_state <= s0;
elsif (clk'event and clk='1') then
case pr_state is
when s0 =>
if start ='1' then nx_state <=s1;
else nx_state <= s0;
end if;
when s1 =>
s_counter <= s_counter + '1';
if (s_counter = "1100") then
nx_state <= s2;
s_counter <=(others =>'0'); -- initializing the counter back to zero
else nx_state <=s1;
end if;
when s2 =>
nx_state<= s0;
end case;
end if;
end process fsmcount;
don <= '1' when (pr_state = s2) else '0';
END ARCHITECTURE arc;

Answer 1

I haven't synthetized it, but I think it should work. I you are not using VHDL2008, modify conditions so that bool types are returned:
ARCHITECTURE arc OF fsm_count IS
type statetype is (s0,s1,s2);
signal pr_state,nx_state: statetype;
signal s_counter: std_logic_vector (3 downto 0);
begin
process(clk) begin if rising_edge(clk) then
if rst then pr_state <= s0; else pr_state <= nx_state; end if;
end if; end process;
process(clk) begin if rising_edge(clk) then
if pr_state/=s1 then s_counter <= (others=>'0');
else s_counter <= s_counter+1; end if;
end if; end process;
process(all) begin
case pr_state is
when s0 =>
if start then nx_state <= s1;
else nx_state <= pr_state; end if;
when s1 =>
if s_counter?=12 then nx_state <= s2;
else nx_state <= pr_state; end if;
when s2 =>
nx_state<= s0;
end case;
end process;
don <= '1' when (pr_state = s2) else '0';
END arc;
EDIT
Alternatively, you can save s2 (i replaced pr_state with sta, nx_state with stn, and s_counter with cnt:
ARCHITECTURE arc OF fsm_count IS
signal idon: std_logic;
type t_st is (s0,s1);
signal sta, stn: t_st;
signal cnt: std_logic_vector (3 downto 0);
begin
process(clk) begin if rising_edge(clk) then
if rst then sta <= s0; else sta <= stn; end if;
end if; end process;
process(clk) begin if rising_edge(clk) then
if sta/=s1 then cnt <= (others=>'0');
else cnt <= cnt+1; end if;
end if; end process;
process(all) begin
case sta is
when s0 =>
if start then stn <= s1; else stn<=sta; end if;
when s1 =>
if idon then stn <= s0; else stn<=sta; end if;
end case;
end process;
idon <= cnt?=12;
don <= idon;
END arc;
Or, you can just use a flag:
ARCHITECTURE arc OF fsm_count IS
signal st, idon: std_logic;
signal cnt: std_logic_vector (3 downto 0);
begin
process(clk) begin if rising_edge(clk) then
if sta/=s1 then cnt <= (others=>'0');
else cnt <= cnt+1; end if;
end if; end process;
idon <= cnt?=12;
process(clk) begin if rising_edge(clk) then
if rst then st <= '0';
elsif not st and start then st <= '1';
elsif st and idon then st <= '0'; end if;
end if; end process;
don <= idon;
END arc;