I am designing a processor based on the Altera DE1 board. My biggest concern is power management. I understand that DE1 board has 3 clock inputs and an external clock input that may be used in my design. However, I would be using only one of these at a time.
Is there any way to turn unused clocks off and only turn them on once they are needed? From the user manual, clock enable for the 3 clock inputs are shorted to Vcc.
The power consumption of the 3 external clock generators are unlikely to be the biggest power drains in a system using the DE1 boards, since you are very likely to have many other unused parts on the DE1 board that will consume even more power than the extra clock generators.
If the a clock is unused inside the FPGA, then the power consumption in the FPGA by having a clock signal input is going to be minimal, since the clock is not distributed internally in the FPGA, thus not burning much power.
Related
Treating the FPGA as a SPI Slave, I've read that on the FPGA it is easier to sample the SPI Clock with the internal clock as opposed to trying to cross the clock domain within the logic.
With that being said, I have a 100Mhz clock and I am trying to implement a 20Mhz SPI clock to read data.
I am having issues with higher SPI clock rates, could it possibly be my internal FPGA clock is too slow?
Which leads to my next question ... Is there a standard to how much faster the FPGA clock should be compared to the SPI clock if one were to take the approach of syncing the SPI clock with the internal FPGA clock?
Thank you
I have a fpga that is taking in serial data at a bit rate of say 4.8 kbps.
Now I am not sure what clock frequency my fpga should run at to properly handle the data.
Will the clock speed simply need to be at minimum 4800 Hz?
It goes the other way round: you first have to determine how many clock cycles you need to process a single input "tick". If one cycle is enough to complete your processing, then 4800 Hz might be fine.
But if you need two cycles, then you would probably go with double speed.
This is a pretty generic answer, but your question is also pretty generic, so this is probably the best you can hope for without enhancing your input.
Will the clock speed simply need to be at minimum 4800 Hz?
Theoretical: yes, practical: no.
Theoretical.
You can receive a 4800 Hz signal with a 4800Hz clock but only if the clock is the exact right frequency. (The 4800 Hz will deviate, no clock is perfect). For that you would need something like a PLL which is in a measurement feedback loop looking at the signal en keeping the clock in step.
Practical.
Much easier is to use e.g. a 1MHz FPGA clock and use over-sampling. Even then you have the same problems as with a dedicated clock: you need to know where the bit boundaries are. Again some sort of clock locking or edge recognition mechanism is required. In fact you have to build the equivalent of a PLL but you can do it all using registers and counters.
When running at 1MHz (which is very slow for an FPGA) you have plenty of clock cycles to process your data.
Both methods depend on the protocol you are using which you did not mention. They are only possible for some type of signals/serial protocols. For example if signals are low or high for many clock cycles that would cause problems for either method.
I would like to know how much current is consumed by multiplication operation in Arduino (ATMega328P) microcontroller. As per ATMega328p datasheet, multiplication operation takes 2 cycles. I have to now convert it to current.
Please let me know how to calculate it. Attached is ATMega328p datasheet for frequency versus current graph.
Multiplication operation didn't consume any energy itself. It doesn't matter if ATmega multiply something or not. If MCU is up and running program (doesn't matter what is he doing - add, subtract, multiply, cycling or just doing nothing (NOP operations)) - it consume some power, and the value of consumption you can extract from your graph (if it is correct).
So, on 5V supply and 16MHz it will consume about 9 mA. This is MINIMAL possible power consumption.
Note, that power consumption of the ATmeaga chip is also depends on the working timers, ADC, SPI and other peripheral components inside the chip. Consumption depends on them if they turned on or not (turned off), if they are clocked and also depends on clock frequency. And consumption will increase with each active peripheral component. Also if you have LEDs connected to pins or power supply, other active components, connected to the ATmega or just on the same board connected to power supply, the power consumption will increase.
I am designing a processor using an Altera DE1 kit.
I will be running test bench to stress the processor.
I want to know if there is any way to measure only the power consumption of my design and neglecting the other power dissipation caused by the DE1 board.
TIA for the answer.
Measure power at an idle state. The idle state can be many things. This needs to be decided by you:
The board operating when the FPGA is not programmed (no bitstream loaded).
FPGA loaded, but you hold down the reset for the logic.
Place the FPGA in some kind of suspended state (sleep mode).
Now that you have your reference power measurement, measure the power with your design running fully. Subtract one from the other, and you will have a result which is close to what you are searching for (The board may consume differently, at each idle state, than it would have been when running normally with your design).
You should be able to replace the 0-Ohm resistor R29 by a shunt resistor and measure the core current of the fpga through that. It's right in series with VCCINT so it should reflect only the current used by the fpga logic.
There's also R30 in series with VCCIO, if you want to include IO power consumption as well.
The resistor names are from this schematic (the only one I could find so far): http://d1.amobbs.com/bbs_upload782111/files_33/ourdev_586508CWZW3R.pdf
I am writing a code using VHDL to convert 24MHz and 12 MHz clock to 8 MHz clock. Can anyone please help me in this coding? Thanks in advance.
Is this for an FPGA? Or something else? Are you really dividing a clock, or just a signal? For a divide by three counter, try this link:
http://www.asic-world.com/examples/vhdl/divide_by_3.html
And for a 2/3:
http://www.edaboard.com/thread42620.html
As Martin has already said, use a clock management device by Xilinx recommendations in order to divide your clock down to a lower rate.
While you might be tempted to implement a clock divider using logic and a counter, you will not obtain good synthesis results.
Here are some tips:
Be sure to closely read and follow recommendations for the clock management hardware for your device. There can be quite a few "gotchas" related to power-up, reset, loss of clock lock, etc.
Make sure that you are operating the clock management device within its specifications. See your device's datasheet for more information (in this case for the S3-A).
Use FPGA Editor to verify correct placement and configuration of your clock management units (i.e. did it end up in the right spot on the chip)
Adhere to recommended practices for feedback clocks, and clock buffering.
Use a DCM or PLL (depending on the family of FPGA) - there's examples in the documentation. If you tell us which family, I might be able to point you more directly.
EDIT:
As you say Spartan 3ADSP - you need to either:
Use the Core Generator Clocking Wizard to create you a VHDL or Verilog file with the components you need in and hope you never need to understand what's going on
Read the libraries guide and the DCM section of the Userguide for that chip and instantiate a DCM on your own and apply the correct generics/parameters to it.
Don't forget to apply a reset pulse to the DCM after configuration has finished 0 and make sure that pulse lasts long enough. The min pulse length is different for each family, I don't recall off the top of my head what it is for that chip, so check the datasheet.