Component declaration error in VHDL - vhdl

Question

I'm trying to declare and use a componenet in a VHDL file, but Quartus II is giving me the following errors:
Error (10482): VHDL error at operacao_mod_datapath.vhd(85): object "i_LD" is used but not declared
Error (10482): VHDL error at operacao_mod_datapath.vhd(86): object "i_IN" is used but not declared
Error (10482): VHDL error at operacao_mod_datapath.vhd(87): object "o_DOUT" is used but not declared
Error (10558): VHDL error at operacao_mod_datapath.vhd(87): cannot associate formal port "o_DOUT" of mode "out" with an expression
The VHDL file of reg_in is correct, and i always declare components like that and Quartus never gives me this error. what is happening?
Below is the code:
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
USE ieee.numeric_std.ALL;
entity operacao_mod_datapath is
port (
i_RESET : IN STD_LOGIC; -- Sinal para resetar a maquina de estados do contador
i_CLOCK : IN STD_ULOGIC; -- Clock
i_LOAD_K : IN STD_LOGIC; -- Sinal para carregar K
i_LOAD_A : IN STD_LOGIC;
i_LOAD_B : IN STD_LOGIC;
i_LOAD_S : IN STD_LOGIC;
i_LOAD_CLEAR : IN STD_LOGIC; -- Sinal para limpar K
i_A : IN UNSIGNED (7 downto 0); -- Entrada A
i_B : IN UNSIGNED (7 downto 0); -- Entrada B
o_OUTS : OUT INTEGER; -- Saida da operação aritmética
o_COMP : OUT STD_LOGIC -- Saída do comparador
);
end operacao_mod_datapath;
architecture arch_1 of operacao_mod_datapath is
component array_multiplier is
port (
i_MULTIPLICAND : in unsigned(7 downto 0); -- data input
i_MULTIPLIER : in integer; -- data input
o_DOUT : out std_logic_vector(15 downto 0)); -- data output
end component;
component k_reg is
port (
i_CLR : IN STD_LOGIC;
i_CLK : IN STD_ULOGIC;
i_DINL : IN STD_LOGIC ; -- Sinal de load para carregar K
i_DINK : IN INTEGER; -- Valor antigo de K
o_DOUTK : BUFFER INTEGER -- saída S da operação de mod
);
end component;
component comparator is
port (
i_DINS : IN INTEGER; -- Entrada S (saída S da alu_mod)
i_DINB : IN UNSIGNED (7 downto 0); -- Entrada B (entrada do usuário)
o_DOUT : OUT STD_LOGIC); -- Saída para informar o resultado da comparação
end component;
component reg_in is
port (
i_LD : IN STD_LOGIC;
i_IN : IN UNSIGNED (7 downto 0);
o_DOUT : OUT UNSIGNED (7 downto 0)
);
end component;
component alu_mod is
port (
i_LD : IN STD_LOGIC; -- sinal de load
i_DINA : IN UNSIGNED (7 downto 0); -- Entrada A
i_DINM : IN STD_LOGIC_VECTOR(15 downto 0); -- entrada do multiplicador
o_DOUTS : OUT INTEGER -- saída S da operação de mod
);
end component;
SIGNAL w_OUT0 : UNSIGNED (7 downto 0);
SIGNAL w_OUT1 : UNSIGNED (7 downto 0);
SIGNAL w_OUT2 : INTEGER;
SIGNAL w_OUT3 : STD_LOGIC_VECTOR (15 downto 0);
SIGNAL w_OUT4 : INTEGER;
SIGNAL w_OUT5 : STD_LOGIC;
begin
u_0: reg_in port map (
i_LD <= i_LOAD_A,
i_IN <= i_A,
o_DOUT <= w_OUT0
);
u_1: reg_in port map (
i_LD <= i_LOAD_B,
i_IN <= i_B,
o_DOUT <= w_OUT1
);
u_2: array_multiplier port map (
i_MULTIPLICAND => w_OUT2,
i_MULTIPLIER => w_OUT1,
o_DOUT => w_OUT3
);
u_3: k_reg port map (
i_CLR => i_RESET,
i_CLK => i_CLOCK,
i_DINL => i_LOAD_K,
i_DINK => w_OUT2,
o_DOUTK => w_OUT2
);
u_4: alu_mod port map (
i_LD => i_LOAD_S,
i_DINA => w_OUT0,
i_DINM => w_OUT3,
o_DOUTS => w_OUT4
);
u_5: comparator port map (
i_DINS => w_OUT4,
i_DINB => w_OUT1,
o_DOUT => w_OUT5
);
o_OUTS <= w_OUT4,
o_COMP <= w_OUT5;
end arch_1;

Answer 1

After looking the code again I found the error:
u_0: reg_in port map (
i_LD <= i_LOAD_A,
i_IN <= i_A,
o_DOUT <= w_OUT0
);
u_1: reg_in port map (
i_LD <= i_LOAD_B,
i_IN <= i_B,
o_DOUT <= w_OUT1
)
The correct is:
u_0: reg_in port map (
i_LD => i_LOAD_A,
i_IN => i_A,
o_DOUT => w_OUT0
);
u_1: reg_in port map (
i_LD => i_LOAD_B,
i_IN => i_B,
o_DOUT => w_OUT1
);

Answer 2

You don't only need to declare the components, but you need to port map them as well. Port mapping is when you decide to route the signals between the various modules that are there in the code. One module's output can be routed as an input to another module and this is what port mapping is and what the tool means by "using".