How the traditional device driver program differs from writing a device driver that support Device Tree ?
In the Linux kernel before device trees were introduced data required by drivers was provided through board files and there would be a board file for each possible board. It was provided from something called as platform data and drivers would be platform driver which are drivers basically not discoverable automatically or enumerated like USB or PCI.
The above approach resulted in a lot of mess and duplication as a lot of the data would of course be common or could be common between boards. For example, a GPIO controller for a particular SoC is not going to be different between boards or require different information at least not primary ones like interrupt id.
Device trees approach have a SoC level dtsi file which is common and all board or module variants inherit them but specify what any differences or additional peripherals to turn off or on.
Functions to parse or read either of them are different. Device trees describe hardware and the primary difference in both of them is how the data is provided and read.
Related
We saw this answer: Direct communication between two PCI devices
Which goes a long way towards answering the question. But we wanted to poke a bit at it, to see if there's any wiggle room.
So, we are making custom PCIe cards, with custom drivers. The only thing outside our control is the chipset in the Server that the cards are plugged into. if we control which two boards we plug in, and both are programmed to talk to each other, such that "raw" data is fine.. and the device drivers are aware of the desire for direct communication.. can you see a way for direct data transfer? Getting creative?
If it is one root complex with multiple ports, then it's possible to have direct endpoint to endpoint communication.
If it's a multi-rooted root complex, then it's not covered by the PCIe specification and vendor-dependent if that feature is implemented. So notice multi-rooted PCIe subsystems in many cases if the bus IDs aren't consecutively numbered. It also depends on the implementation of the enumeration procedures if additional root complexes start their first bus ID by multiples of e.g. 64.
I'm working on a project that requires reading and writing data to an SD card, and I want to make the algorithms that evaluate incoming data in hardware. I found out that the only way to read/write to an SD card through my FPGA board would be to implement a processor and then write software, which would defeat the purpose of using the FPGA board in the first place.
So, I've decided that I'm going to use my Arduino Yun to read information from a micro SD card, and then encode it into binary and send each piece of data to the FPGA in UART.
(The data consists of base pairs in DNA, so I'm making each base pair take up four bits, and making it into more of a logic map rather than any kind of ASCII map or anything - the details of this choice aren't very important, but it makes using UART and binary valid for this application.)
However, the only thing that can carry the UART signal for the FPGA board is the micro USB slot, so I have to plug a cable into that, and the other end of it into the USB Host of the Arduino.
I've come to understand that the Yun's USB Host is connected solely to the on-board Linux processor, and while I understand that this means that I need to install various packages onto the micro SD card that I've used to extend the Yun's memory, I'm not sure what packages to use, or even how to go about using them.
Could anyone point me in the direction of libraries/packages that I should install, and what sort of code I should write to implement this functionality?
Any help would be greatly appreciated.
Please let me know if I've left out any details!
Example:
Let's assume there is a Nios running on a FPGA that sends randomly (or every second) a string to an attached display over the SPI interface. On the other hand there is the FPGA code that monitors a pushbutton. Every press on this button should send a string to the same attached display.
Question:
How works the interaction (or communication) between the FPGA and Nios in general or in such described case? How is it possible to 'inform' Nios that the pushbutton is pressed when this code is running under the FPGA code? Maybe there is a documentation about this topic to get an idea how it works...
Thanks in advance
Low speed or high speed?
For low speed, plug a GPIO core with enough I/O "pins" into the NIOS system and rebuild it. Wire your hardware to those pins, and use the GPIO driver code to access them. Done. Buttons count as low speed. SPI can too, though you'll probably find a much better SPI peripheral for NIOS, so I'd use that.
For high speed, you need to design a peripheral (IP core) that interfaces to whatever bus the NIOS system uses, and provides all the registers, memory, interrupt sources etc you need to interface to your VHDL hardware. There are plenty of example peripherals you can use as a starting point. Then you get to write the driver software to access that peripheral, again, starting from sample code.
This is a much more complex project, and while it's much faster than GPIO, you find "high speed" is relative; any embedded CPU is appallingly slow compared to custom hardware. We're not talking about factors of 2 here but orders of magnitude.
EDIT : Whichever approach you use, as described above, interacting with the hardware from the software side is best done through the driver software.
If you're in the situation where you have to write your own driver, then you declare variables to match each accessible register or memory block (represented by an array variable). Often the vendor tools can create a skeleton driver for you, from either the VHDL code or some other description. I don't know how Altera/Nios tools are set up but they surely have tutorials to teach you their approach.
If you have an Ada compiler you can declare these variables at package scope, to maintain proper abstraction and information hiding. But if you have to use C, with no packages, you are probably stuck with global variables.
You fix each variable at whatever physical address your hardware maps them to, and you must declare them "volatile" so that accesses to them are never optimised into registers.
If your hardware can interrupt the CPU, you have to write an interrupt handler function, with pragmas to tell the compiler which interrupt vector it should be connected to. You'll need to get the exact details from your own compiler documentation and examples of driver code for other peripherals.
I would start here:
https://www.altera.com/support/support-resources/design-examples/intellectual-property/embedded/nios-ii/exm-developing-hal-drivers.html
with sample code and a short "Guidelines" document
and use the NIOS software handbook for more depth.
To help find what you're looking for, apparently Altera use the terms "HAL" (Hardware Abstraction Layer) to describe the part of the driver that directly accesses the hardware, and "BSP" (Board Support Package) for the facilities that allow you to describe your hardware to the tools - and to your software team. Any tools to build a skeleton driver will be associated with the BSP : I see a section called "Creating a new BSP" in the software handbook.
I want to program an FPGA on a board that has a socket (zif etc or whatever is applicable) for said FPGA, from which it can be removed and reattached without soldering. I want to know where I can get a board suitable for programming an FPGA in this way?
Once the FPGAs have been programmed they will be attached to another different PCB via solder.
I wish to essentially program the FPGA in a similar way that it is possible to program an EPROM.
I wish to use VHDL if at all possible.
FPGAs are not programmed like an EPROM - their internals are completely volatile. In system use, they are 'configured' from some other non-volatile memory. For example, many can interface directly to a standard serial flash device to load that configuration.
This non-volatile memory is the device which you need to "program" in some fashion. For example:
before soldering, using some external agency
using JTAG (if it has such an interface).
Or, you can load a configuration into the FPGA over JTAG which then allows you to program the flash using the FPGA!
It sounds as if you've misunderstood a thing or two. An STM32F103 is a microcontroller, that is, a processor with built-in memory, I/O and similar, and is typically programmed in C or C++.
VHDL (a Hardware Description Language) is used to program FPGAs (amongst others). There is a fundamental difference in the two types of chips. A processor is a "static" chip, which executes a program instruction by instruction, whereas in an FPGA the chip hardware itself is programmable - you (by using for instance VHDL) describe the actual connectivity and functionality of the chip, and essentially create numerous small, customized and application-specific processors.
You should probably first of all learn a bit more about the differences between the two types of chips - then have a look at for instance some of Digilents FPGA boards.
Also, programming a chip in one board, unsoldering it, and soldering it to another is not a good idea. Both microcontrollers and FPGAs today should be soldered to their final board, and then programmed (for instance over JTAG) - I'm sorry to say that what you are proposing doesn't really make much sense - and if you look at the pin count and packages of today's chips you might see why.
I seem to be under the impression that FPGAs can be updated while the chip is running; and I need to know if that is correct or not.
It seems to be from what I've read that you can change the FPGA netlist on demand the same way you can change the program that's running on a processor. Yes I know that an FPGA is not a processor.
Is my assumption correct, and if not then how come?
Most of the time, you load the configuration for the entire FPGA in one go, and all logic stops running during the reconfiguration process.
It sounds like you want to reload a subset of the FPGA, while the remainder continues running. You would need a device with special support for partial reconfiguration. There's more information on Wikipedia.
==> EDIT: I stand corrected: EETimes article on partial reconfiguration
You will generally need to reset the FPGA so that it can be reprogrammed.
At a system level reconfiguration is possible. You can have a software application running on a PC or embedded system that reprograms the FPGA as needed. Depending on the application or software license, you can program different FPGA designs easily. You cannot, however, significantly alter the design structure, such I/Os, logic cells, DSP configs, memory blocks, etc.
FPGAs have a bunch of logic cells that need to be initialized by a stream of configuration bits. This stream of bits usually comes from a flash chip located off the device, although some devices have the flash memory on-board.
Partial Reconfiguration means the ability to configure just some of the logic cells while the rest are in use. This is specific to particular models.
Total reconfiguration is possible even if your device doesn't support it - you would need to reprogram the flash chip and then issue a Reset or reload command when done.
Some devices have more than one configuration image in the configuration flash. The device will load the first image, and if it doesn't like it, it will load the second (or subsequent) images. This can be for redundancy, or difference feature sets.
Some of the SOC FPGAs (like Xilinx Zynq) use the microprocessor core to load the FPGA. In this case, the microprocessor core can change the FPGA as much as it wants while running.
Yes I know that an FPGA is not a processor.
An FPGA is is a type of processor, but it is not a type of CPU.
Most FPGAs only have volatile storage so you have to update them whilst they're on. This doesn't mean that you can change their operation any time you want. That's dynamic reconfiguration and only supported by a subset of FPGAs.