How can I change the max_brightness value in the LED subsystem sysfs parameter. It always shows 255. Can it be changed to higher number say 65536 from within the driver code so that whenever I do cat brightness I get the max value I set in the code?
Does the 0-255 value needs to be mapped to the actual brightness values of the led in the driver code?
Example: if the max brightness value of the LED is AAAA that means value x can be mapped as (x * 65536/255)
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I'm having some difficulty getting PCNT pulse counting working with a prototype ESP32 device board.
I have a water level sensor (model D2LS-A) that signals state by the frequency of a square wave signal it sends to GPIO32 (20Hz, 50Hz, 100Hz, 200Hz, 400Hz).
Sadly, the PCNT counter stays at 0.
To troubleshoot, I tried putting GPIO32 in ADC mode (attenuation 0, 10-bit mode) to read the raw signal (sampling it many times a second), and I'm getting values that I would expect (0-1023). But trying the same thing using digital GPIO mode, it always returns 0, never 1 in all the samples.
Since the PCNT ESP IDF component depends on reading the pin digitally, the counter never increments past 0.
So the real problem I'm having is: why aren't the ADC readings (between 0-1023) translating to digital readings of 0-1 as one would expect?
As per the datasheet of Atmega328, Timer0 fast PWM mode can be selected by setting WGM02:00 to either 011 or 111.
When we set Fast PWM mode using 111, TOV Flag set on TOP. Also TOP is equal to OCR0A. Now ON time of PWM is controlled using OCRA. When compare match occurs, OCA0 is cleared (COM0A1:COM0A0 = 10) and it is set at the bottom.
Now my question is if TCNT clears after reaching TOP (that is nothing but OCR0A), how can we alter On time with WGM02:00=111? I am not quite clear from data sheet. Even waveforms are also little confusing. Or is it that TCNT always counts from 0x00 to 0xff irrespective of TOV flag in this case?
Since OCRA is in use, you have to use the other OC registers, e.g. OCRB. OCA will still follow the directions given to it by COM0A, but is significantly less useful for that.
While using the output compare unit register (OCR0A) to define the top value of the counter (WGM02:WGM00=111), you can only toggle the logical level at the corresponding pin (OCA0) when a compare match between TCNT0 & OCRA0 occurs. Hence, you can't control the duty cycle (always 50%). This is just like the ctc mode, except that the double buffering feature of the output compare unit is enabled in fast PWM mode. Look at the datasheet, the last paragraph in the description of fast PWM mode:
A frequency (with 50% duty cycle) waveform output in fast PWM mode can
be achieved by setting OC0x to toggle its logical level on each
compare match (COM0x1:0 = 1). The waveform generated will have a
maximum frequency of fOx0 = fclk_I/O/2 when OCR0A is set to zero.
This feature is similar to the OC0A toggle in CTC mode, except the
double buffer feature of the Output Compare unit is enabled in the
fast PWM mode.
However, you can use timer 1 to control the frequency and the duty cycle, by setting the input capture unit register (ICR1) to define the TOP value of the counter, and then the output compare unit register (OCR1A) will be free to make the corresponding pin (OC1A) take action (set or clr) when a compare match occurs.
I was looking at Atmega328. Atmel has given lot of features in timer section. But I observed that Output Compare A and Output Compare B modes of operation depends on WGM bits and cannot be set differently for both. For Example: I cannot select OCA pin in Fast PWM mode and OCB in Normal mode/CTC mode. Either both have to be in normal mode or both in fast PWM or other modes.
Can anyone confirm this? May be atmel could have added a feature where in both OCA and OCB be operated in independent modes.
Since both OCxA and OCxB use the same counter, it cannot be used it in different counting modes simultaneously. One single value cannot in the same time count repeatedly from zero to top, and in the same time to top and then downward to zero, or count to particular independent value (CTC). It has no sense.
But using COMxxx bits in TXCCRxA, you can configure compare match unit to be not connected to the output, therefore, to be used as if in "Normal mode".
When WGM bits set to 111 you can use the timer in mixed PWM/CTC mode: timer will count up to OCRA value, while OCRB (in range 0...OCRA) will be used to generate PWM output.
In Timer1 you can set WGM bits to 1110 to enable CTC up to value of the ICR1 register, while both outputs could be used to generate PWM waveform, you can disconnect any PWM output in COM1xx bits, and use it as "normal", to generate the interrupt request, without value output to the OC1x pin.
In 8086, 20-bit address is generated with two 16-bit registers by using segmentation. The first 16bit address is multiplied by 10 and the result will be added to second 16bit address.
when multiplied by 10 it will generate a 5digit HEXA number which is 20bit long.
where will this intermediate result of 20bit (obtained when multiplied by 10) be stored?
Nowhere. The address appears on the corresponding pins (AD0-AD19) of the chip when it needs to access memory. The calculation is performed internally with dedicated logic. For example there is no actual multiplication by 0x10: the segment bits are directly paired to higher-numbered bits of the offset in corresponding adder (item 3 here).
I'm currentyl building something like a tiny software audio synthesizer on Window 7 in c++. The core engine is running and upon receiving midi events it plays notes, changes programmes, etc. What puzzles me at the moment is where to put the 0 db reference sound pressure level of the output channels.
Let's say the synthesizer produces a sinewave with 440 Hz with an amplitude of |0.5f| . In order to calculate the sound level in db I need to set the reference level (0 db). Does anyone know something like a default for this?
When decibel relative to full scale is in question, AKA dBFS, zero dB is assigned to the maximum possible digital level. A quote from Wiki:
0 dBFS is assigned to the maximum possible digital level.[1] for
example, a signal that reaches 50% of the maximum level at any point
would peak at -6 dBFS i.e. 6 dB below full scale. All peak
measurements will be negative numbers, unless they reach the maximum
digital value.
First you need to be clear about units. dB on its own is a ratio, not an absolute value. As #Roman R. suggested, you can just use 0 dB to mean "full scale" and then your range will be 0 dB (max) to some negative dB value which corresponds to the minimum value that you are interested in (e.g. -120 dB). However this is just an arbitrary measurement which doesn't tell you anything about the absolute value of the signal.
In your question though you refer to dB SPL (SPL = Sound Pressure Level), which is an absolute unit. 0 dB SPL is typically defined as 20 µPa (RMS), which is around the threshold of human hearing, and in this case the range of interest might be say -20 dB SPL to say +120 dB SPL. However if you really do want to measure dB SPL and not just an arbitrary dB value then you will need to calibrate your system to take into account microphone gain, microphone frequency response, A-D sensitivity/gain, and various other factors. This is non-trivial, but essential if you actually want to implement some kind of SPL measuring system.