I have this code:
architecture Behavioral of BlockName is
signal t: std_logic;
signal c : std_logic_vector (1 downto 0);
begin
process (reset, clk) begin
if (reset = '1') then
t <= '0';
c <= (others=>'0');
elsif clk'event and clk='l' then
if (c = din) then
t <= NOT(t);
c <= (others=>'0');
else
c <= c + 1;
end if;
end if;
end process;
dout <= t;
end Behavioral;
This code's role is to divide the frequency when it gets input (clock + value) and outputs a divided frequency.
Now my questions:
What does this c <= (others=>'0'); mean ?
What value does t get here t <= NOT(t); ? the last t value? does the <= work as = ?
c <= (others=>'0'); is equivalent to c <= "00";
t <= not(t); assigns to t the opposite of the current value in t.
= is an equality comparison in VHDL.
<= is signal assignment in VHDL.
since 'C' is taken as a vector and to store every bit of it with zero 'c <= (others=>'0');' was used and the concept of blocking and non blocking signals is not present in VHDL. here '=' is used to compare and '<=' is used to assign the signal.
In the your code 't' is declared as a signal and a signal will be updated at the end of the every iteration of the process block. so in the statement 't <= NOT(t);' the value of the t is still the old value and will be updated at the end of the current simulation tick.
Related
Please understand my very low skill-set on the code. I am trying to learn to be better.
Using DE0 Nano board, I am trying to write VHDL to simulate all available LEDs on the board (8 of them)
I labeled them LED0 ~ LED7. Using 50 MHZ and 1/2 s counter, I wanted to operate individual LEDs in order.
For example, if these individual bits represents on and off of the LEDs.
1|0|0|0|0|0|0|0 -> 0|1|0|0|0|0|0|0 -> 0|0|1|0|0|0|0|0 and so on. At the end, counter would reset back to 0 to repeat the sequence again.
Please view my code below with these questions/issues.
1) I get one 1/2 s pause after 8th LED. Why? How do I fix this?
2) Even if i put the variable counter as 8, it repeats as 16 thus I had to implement the reset of the counter to 0. (marked as question 2 in the code)
3) Is there any better way to write these codes? It is completely messy. Could you give tips on any other function or method I can use to shorten this codes?
Please let me know if any questions!
THANKS A LOT FOR THE HELP.
entity ledtest is
port(
clk_50mhz : in std_logic ;
reset_btn : in std_logic;
green_led : out std_logic_vector(7 downto 0)
);
end entity;
architecture behave of ledtest is
signal clk_1hz : std_logic ;
signal scaler : integer range 0 to 25000000 ;
signal counter : integer range 0 to 8;
signal LED : std_logic_vector(7 downto 0);
begin
clk_1hz_process : process( clk_50mhz , reset_btn )
begin
if (reset_btn = '0') then
clk_1hz <= '0';
scaler <= 0;
counter <= 0;
elsif(rising_edge(clk_50mhz)) then
if (scaler < 25000000) then
scaler <= scaler + 1 ;
clk_1hz <= '0';
else
scaler <= 0;
clk_1hz <= '1';
counter <= counter + 1;
if (counter >= 8) then --------question 2
counter <= 0;
end if;
end if;
end if;
end process clk_1hz_process;
blinking_process : process (clk_1hz,reset_btn)
begin
if (reset_btn = '0') then
LED(0) <= '0';
elsif rising_edge(clk_1hz) AND counter = 1 then
LED(0) <= not LED(0) ;
LED(7) <= '0' ;
elsif rising_edge(clk_1hz) AND counter = 2 then
LED(1) <= not LED(1) ;
LED(0) <= not LED(0) ;
elsif rising_edge(clk_1hz) AND counter = 3 then
LED(2) <= not LED(2) ;
LED(1) <= not LED(1) ;
elsif rising_edge(clk_1hz) AND counter = 4 then
LED(3) <= not LED(3) ;
LED(2) <= not LED(2) ;
elsif rising_edge(clk_1hz) AND counter = 5 then
LED(4) <= not LED(4) ;
LED(3) <= not LED(3) ;
elsif rising_edge(clk_1hz) AND counter = 6 then
LED(5) <= not LED(5) ;
LED(4) <= not LED(4) ;
elsif rising_edge(clk_1hz) AND counter = 7 then
LED(6) <= not LED(6) ;
LED(5) <= not LED(5) ;
elsif rising_edge(clk_1hz) AND counter = 8 then
LED(7) <= not LED(7) ;
LED(6) <= not LED(6) ;
end if;
end process blinking_process;
green_led(0) <= LED(0);
green_led(1) <= LED(1);
green_led(2) <= LED(2);
green_led(3) <= LED(3);
green_led(4) <= LED(4);
green_led(5) <= LED(5);
green_led(6) <= LED(6);
green_led(7) <= LED(7);
end behave;
If your readers squint real hard they can treat the original post as one question and two issues. (A questions is singular.)
Please view my code below with these questions/issues.
1) I get one 1/2 s pause after 8th LED. Why? How do I fix this?
There are 9 counter values (0 to 8) and only 8 LEDs (7 downto 0). No assignments occur in the half second between assigning counter to 0 and incrementing by 1 again.
2) Even if i put the variable counter as 8, it repeats as 16 thus I had to implement the reset of the counter to 0. (marked as question 2 in the code)
This issue is tied in with 1). The requirement for evaluating counter greater than or equal to 8 is caused by assigning counter to 8, again there are 9 values and only 8 LEDs. Note that's a synchronous load to 0 and not an asynchronous reset.
3) Is there any better way to write these codes? It is completely messy. Could you give tips on any other function or method I can use to shorten this codes?
Because you're attempting to go directly to FPGA instead of simulating the focus on tips should relate to the question 1) and how to fix it. There are also some synthesis issues, here gating clocks by adding enables to the conditions in if statement elsif alternatives. There's also the issue of design specification complexity and the amount of debugging effort associated with the number of lines of code.
First there are flip flops for all LED elements as well a counter. We can reduce the number of flip flops to one for each LED element by using a ring counter (not to be confused with a Johnson counter).
Assignments to green_led (the std_logic_vector) can be from LED (the std_logic_vector) instead of element by element. There's a one to one correspondence between element indices on both side of the assignment(s).
Also to allow simulation you could virtualize the time interval of a half second loaded into scalar. This has the effect of having fewer clocks represent a half second. The idea is simulation doesn't have to take the 10+ seconds of 100 million clock transitions per second (rising and falling edges).
Throw all these together and the code is changed to look like:
library ieee;
use ieee.std_logic_1164.all;
entity ledtest is
generic (half_second: integer := 24999999); -- zero identity
-- the generic allows fewer clocks per second for simulation
port (
clk_50mhz: in std_logic;
reset_btn: in std_logic;
green_led: out std_logic_vector(7 downto 0)
);
end entity;
architecture behave of ledtest is
signal clk_1hz: std_logic;
signal scaler: integer range 0 to half_second;
-- signal counter: integer range 0 to 8; -- DELETED
signal ring_counter: std_logic_vector (7 downto 0); -- ADDED
signal LED: std_logic_vector (7 downto 0);
signal LED0I: std_logic; -- ADDED
begin
LED0I <= '1' when LED = "00000000" else
'0';
clk_1hz_process:
process (clk_50mhz, reset_btn)
begin
if reset_btn = '0' then
clk_1hz <= '0';
scaler <= 0;
-- counter <= 0;
elsif rising_edge(clk_50mhz) then
if scaler /= half_second then
scaler <= scaler + 1;
clk_1hz <= '0';
else
scaler <= 0;
clk_1hz <= '1';
-- counter <= counter + 1;
-- if counter >= 8 then --------question 2
-- counter <= 0;
-- end if;
end if;
end if;
end process clk_1hz_process;
blinking_process:
process (clk_1hz, reset_btn)
begin
if reset_btn = '0' then
LED <= (others => '0');
-- LED(0) <= '0';
elsif rising_edge(clk_1hz) then
LED <= LED(6 downto 0) & (LED(7) or LED0I);
-- ring counter with a roulette ball lauch after reset
-- elsif rising_edge(clk_1hz) AND counter = 1 then
-- LED(0) <= not LED(0);
-- LED(7) <= '0';
-- elsif rising_edge(clk_1hz) AND counter = 2 then
-- LED(1) <= not LED(1);
-- LED(0) <= not LED(0);
-- elsif rising_edge(clk_1hz) AND counter = 3 then
-- LED(2) <= not LED(2);
-- LED(1) <= not LED(1);
-- elsif rising_edge(clk_1hz) AND counter = 4 then
-- LED(3) <= not LED(3);
-- LED(2) <= not LED(2);
-- elsif rising_edge(clk_1hz) AND counter = 5 then
-- LED(4) <= not LED(4);
-- LED(3) <= not LED(3);
-- elsif rising_edge(clk_1hz) AND counter = 6 then
-- LED(5) <= not LED(5);
-- LED(4) <= not LED(4);
-- elsif rising_edge(clk_1hz) AND counter = 7 then
-- LED(6) <= not LED(6);
-- LED(5) <= not LED(5);
-- elsif rising_edge(clk_1hz) AND counter = 8 then
-- LED(7) <= not LED(7);
-- LED(6) <= not LED(6);
end if;
end process blinking_process;
green_led <= led;
-- green_led(0) <= LED(0);
-- green_led(1) <= LED(1);
-- green_led(2) <= LED(2);
-- green_led(3) <= LED(3);
-- green_led(4) <= LED(4);
-- green_led(5) <= LED(5);
-- green_led(6) <= LED(6);
-- green_led(7) <= LED(7);
end architecture behave;
(Also note the default generic value scalar is reset and loaded to has been decremented to include the unity 0 in the 250,000,000 clocks be half second. The equality test for half_second is simpler than using magnitude comparison.)
Using a ring counter reduces complexity and side steps the issue of a counter range of 9.
The ring counter has a flourish added, the reset value is all '0's which are detected by signal LED0I which is used to start the ring counter after reset. It prevents all the LEDs from being lit during reset.
You can use a testbench with the number of clocks comprising a half second to a much smaller number allowing fast simulation with small waveform dump files:
library ieee;
use ieee.std_logic_1164.all;
entity ledtest_tb is
end entity;
architecture foo of ledtest_tb is
signal clk: std_logic := '0';
signal reset_btn: std_logic := '1';
signal green_led: std_logic_vector (7 downto 0);
begin
DUT:
entity work.ledtest
generic map (half_second => 7)
port map (
clk_50mhz => clk,
reset_btn => reset_btn,
green_led => green_led
);
CLOCK:
process
begin
wait for 0.5 sec / 7;
clk <= not clk;
if now > 19 sec then
wait;
end if;
end process;
STIMULUS:
process
begin
wait for 0.5 sec;
reset_btn <= '0';
wait for 0.5 sec;
reset_btn <= '1';
wait;
end process;
end architecture;
And that gives:
You could eliminate the generic map in the testbench instantiation of ledtest to demonstrate the difference in simulation time and dump file size inherent with simulating every clock transition with a 50 MHz clock. The idea here is it's easier to troubleshoot a simulation than it is to guess from what you can see (here the LEDs). Because the code description was simplified there was debugging required using the original code as a starting point. It did rely on a knowledge of digital electronics and VHDL.
The simulation was done with ghdl and gtkwave.
I have some Filter coefficients in BRAM those coefficients need to be written into an array to perform convolution. I have created an array using type and assigned it to a signal. That signal I have port mapped to DATA_OUT of BRAM. it's giving an error "expecting STD_LOGIC_VECTOR"
I've tried writing the data in an array with for loop. It results in an error "indices is not a STD_LOGIC_VECTOR"
my type declaration
TYPE coeff_pipe IS ARRAY(0 TO 15) OF std_logic_vector(7 downto 0);
Signal coeff:coeff_pipe;
my for loop is like this
for i in 0 to loop
coeff(i) <= data_out_BRAM(i); end loop;
Help me with suitable changes in my code to make it work
You mix the for loop behavior in a coding language (C) and in a hardware descritpion language (VHDL). In a coding language, if you write a for loop, processor will execute the content of the loop several times in row sequentially (one after one). In an HDL, for loop is used to instanciate several times the same circuit with different inputs/outputs. There is no time notion in a for loop.
In your case, you have to use a sequential process and increment your BRAM address :
process(clk, rst)
begin
if rst = '1' then
addr_BRAM <= (others => '0');
addr_BRAM_d <= (others => '0');
ram_init_en <= '1';
ram_init_en_d <= '0';
coeff <= (others => (others => '0'));
elsif rising_edge(clk) then
addr_BRAM_d <= addr_BRAM ; -- Delay of 1 clk cycle
ram_init_en_d <= ram_init_en; -- Delay of 1 clk cycle
-- Init done
if addr_BRAM = x"1111" then
ram_init_en <= '0';
end if;
-- Increment BRAM address
if ram_init_en = '1' then
addr_BRAM <= std_logic_vector(unsigned(addr_BRAM) + 1);
end if;
-- Get data one cycle after set address because a BRAM doesn't answer instant, it answers in one clk cycle.
if ram_init_en_d = '1' then
coeff(to_integer(unsigned(addr_BRAM_d))) <= data_out_BRAM;
end if;
end if;
end process;
i am trying to write a code but i get error, i dont understand that, i am new to vhdl, any help would be appreciated.
code:
entity counter is
port
(
upp_down : in std_logic;
rst : in std_logic;
pressed : in std_logic;
count : out std_logic_vector(3 downto 0)
);
end entity;
architecture rtl of counter is
signal count_value: std_logic_vector(3 downto 0);
begin
process (rst,pressed,upp_down)
begin
if(rst'event and rst = '0') then
count <= "0000";
else
if(pressed'event and pressed = '0' ) then
if(upp_down = '1') then
count_value <= count_value + 1;
elsif(upp_down = '0') then
count_value <= count_value - 1;
end if;
end if;
end if;
end process;
count <= count_value;
end rtl;
Errors:
Error (10820): Netlist error at counter.vhd(28): can't infer register for count_value[1] because its behavior depends on the edges of multiple distinct clocks
Error (10822): HDL error at counter.vhd(28): couldn't implement registers for assignments on this clock edge
The first problem is that you're trying to use the edge of two different 'clocks' in one process. A particular process can only respond to one clock.
The second problem is that your code does not translate into any real-world hardware. There's nothing in the FPGA that can respond to there not being an edge of a clock, which is what you have described with your if(rst'event and rst = '0') then else structure.
Nicolas pointed out another problem (which your compiler didn't get as far as), which is that you're assigning count both inside and outside a process; this is not allowed, as signals can only be assigned in one process.
Generally the type of reset it looks like you're trying to implement would be written as in the example below:
process (rst,pressed,upp_down)
begin
if(rst = '0') then
count_value <= "0000";
elsif(pressed'event and pressed = '0' ) then
if(upp_down = '1') then
count_value <= count_value + 1;
elsif(upp_down = '0') then
count_value <= count_value - 1;
end if;
end if;
end process;
count <= count_value;
The reason for changing the reset to affect count_value, is that without this, the effect of your reset would only last one clock cycle, after which the count would resume from where it left off (Thanks #Jim Lewis for this suggestion).
In addition to your compile errors, you should try to use the rising_edge() or falling_edge() functions for edge detection, as they behave better than the 'event style.
The reset can be more easily implemented using count_value <= (others => '0'); this makes all elements '0', no matter how long count is.
Lastly, it looks like you're using the std_logic_arith package. There are many other answers discouraging the use of this package. Instead, you should use the numeric_std package, and have your counter of type unsigned. If your output must be of type std_logic_vector, you can convert to this using a cast: count <= std_logic_vector(count_value);.
One more thing, I just noticed that your counter is not initialised; this can be done in the same way as I suggested for the reset function, using the others syntax.
"count" can't be assigned inside and outside a process.
count <= "0000"; <-- inside process
count <= count_value; <-- outside process.
You should do "count <= count_value;" inside your process :
entity counter is
port
(
upp_down : in std_logic;
rst : in std_logic;
pressed : in std_logic;
count : out std_logic_vector(3 downto 0)
);
end entity;
architecture rtl of counter is
signal count_value: std_logic_vector(3 downto 0);
begin
process (rst,pressed,upp_down)
begin
if(rst'event and rst = '0') then
count <= "0000";
else
if(pressed'event and pressed = '0' ) then
if(upp_down = '1') then
count_value <= count_value + 1;
elsif(upp_down = '0') then
count_value <= count_value - 1;
end if;
count <= count_value;
end if;
end if;
end process;
end rtl;
I have searched about this problem but it all seemed Greek to me so I came here as last effort.I have the following VHDL code that I want to be implemented on an fpga.
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.std_logic_arith.all;
use work.conversions.all;
entity counter is
port ( clk_in: in std_logic; --new clock
target : in std_logic_vector(7 downto 1); --Set the target with the switches (SW7-SW1)
start : in std_logic; --Start/pause (SW0)
rst : in std_logic; --Reset (BT0)
LD : out std_logic_vector(7 downto 1); --Leds show the target at binary (LD7-LD1)
LD0 : out std_logic; --LD0 indicates thw the limit has been reached
seg : out std_logic_vector(7 downto 0); --7 segment display
digit : out std_logic_vector(3 downto 0)
);
end counter;
architecture Behavioral of counter is
begin
process(clk_in,target,rst)
variable timer : natural := 0;
variable counter : natural := 0;
variable display_counter : natural range 0 to 4 := 0;
begin
LD0 <= '0';
LD <= target; --Show the target at the leds
digit <= "1110"; --Last digit active
seg <= "00000011"; --Show zero
<--->if(rst='1') then --Reset counter
counter := 0;
timer := 0;
digit <= "1110"; --Last digit active
seg <= "00000011"; --Show zero
LD0 <= '0';
elsif rising_edge(clk_in) then
if(start = '0') then --Pause
--counter := counter;
elsif(counter = conv_integer(unsigned(target))) then --timer limit has been reached
LD0 <= '1';
else
counter := counter + 1;
display_counter := display_counter + 1;
if(counter rem 10 = 0) then --one second has elapsed (10Hz cycle)
timer := timer + 1; --increase timer
end if;
case display_counter is --Select which digits are gonna be activated and with what
when 1 =>
seg <= int2led(timer/1000);
if(int2led(timer/1000) = "00000000") then
digit(3) <= '1';
else
digit(3) <= '0';
end if;
when 2 =>
seg <= int2led((timer/100) mod 10);
if(int2led((timer/100) mod 10) = "00000000") then
digit(2) <= '1';
else
digit(2) <= '0';
end if;
when 3 =>
seg <= int2led((timer/10) mod 10);
if(int2led((timer/10) mod 10) = "00000000") then
digit(1) <= '1';
else
digit(1) <= '0';
end if;
when others =>
seg <= int2led(timer/10);
if(int2led(timer/10) = "00000000") then
digit(1) <= '1';
else
digit(1) <= '0';
end if;
end case;
if (display_counter = 4) then --reset the display counter from time to time
display_counter := 0;
else
display_counter := display_counter;
end if;
end if;
end if;
end process;
end Behavioral;
The problem is at if(rst='1') then. Can anyone explain to me in plain English why is this happening and a solution to it so I won't have the same kind problems again? Thanks in advance
You have default signal assignments before the if rst='1' then clause.
That means, when rst returns to 0 (in simulation) these default assignments will execute, and delete the reset values of those signals.
XST is telling you that the hardware can't actually do that.
The solution is to delete those default assignments, which will restore this process to a standard form. Then think carefully about what they were for and how to keep their functionality if you need to.
The traditional place for such assignments is immediately after the elsif rising_edge(clk) then clause, where they will be executed on every clock edge (provided Rst is low) then overridden by any other assignments that are executed yb the process.
I have this code for a lifo memory and I don't understand why on 27 line (if(last = n-2) then full <= '1'; end if;) the last signal it's not equal to n-1.
If anyone could explain it to me I would really appreciate.
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity lifo is
generic(n : natural := 4);
port(Din : in std_logic_vector(3 downto 0);
Dout : out std_logic_vector(3 downto 0);
wr : in std_logic;
rd : in std_logic;
empty, full : out std_logic;
clk : in std_logic);
end entity lifo;
architecture arh of lifo is
type memorie is array(0 to n-1) of std_logic_vector(3 downto 0);
signal mem : memorie := (others => (others => '0'));
signal last : integer range -1 to n-1;
begin
process(clk)
begin
if (rising_edge(clk)) and (wr = '1') then
if (last = n-1) then null;
else
if(last = n-2) then full <= '1'; end if;
if(last = -1) then empty <= '0'; end if;
mem(last + 1) <= Din;
last <= last + 1;
end if;
elsif (rising_edge(clk)) and (rd = '1') then
if(last = -1) then null;
else
Dout <= mem(last);
last <= last - 1; full <= '0';
if(last = -1) then empty <= '1'; end if;
end if;
end if;
end process;
end architecture arh;
The last is in range -1 to n-1, and when last is n-1 then it indicates full LIFO, and full must be high ('1').
When a write is accepted, then last is incremented by 1 with last <= last + 1. On the same rising clk edge it is determined if full should go high, which is the case if this write will make the LIFO full. After the write, then last has the value last+1 (the +1 when write is accepted) and LIFO is full if is equals n-1 (with n-1 indicating full). So the condition for full after this write is last+1=n-1, which is then written as last = n-2.
In addition, it is possible to improve the code in several ways if it does not work right away, e.g. single rising_edge(clk), add reset, skip the null statements through negated condition, add handling of write and read operation in same cycle, remove dead code (the final if).