How to implement CMake configure_file command in Makefile? - makefile

I think everybody knows this excellent CMake command:
configure_file(
${CMAKE_CURRENT_SOURCE_DIR}/version.h.cmake
${CMAKE_CURRENT_BINARY_DIR}/version.h
)
But I have to implement that in Makefile. Could you please help me? How to do it?
Configuration file (version.h) is very simple:
#ifndef _VERSION_H_
#define _VERSION_H_
#define VERSION_MAJOR #VERSION_MAJOR#
#define VERSION_MINOR #VERSION_MINOR#
#define VERSION_BUILD #VERSION_BUILD#
#define VERSION_REVISION #VERSION_REVISION#
#endif // _VERSION_H_

This won't work. Well it might be, but it will be a hassle. These config.h files are made to communicate the result from a configure tool (configure from Autotools, CMake etc.) to the compiler.
When you use Makefiles, you can simply attach necessary flags or variables to the C(++) compiler call (with -D). There is no need to add the complexity of a config.h.

Related

Run preprocessor and keep directives

Is there a way I can run gcc -E to run the preprocessor but also to keep the #define, #include, other directives in the output (possibly as comments)? I thought I remembered seeing an option for this but I can't find it in the GCC Preprocessor Options page. I need this to track down where things are going wrong in a complex case involving lots of include files and macros.
The relevant options are listed under -dCHARS. -dD outputs macro definitions (both #define and #undef directives), -dI outputs #include directives, and they can be combined to -dDI.

conditional compliation based on variable into makefile

Inside my C/C++ code I would like to include or not a file depending on different compilation.
For the moment I use this:
#ifndef __x86_64__
#include <myLib.h>
#endif
this gives me the possibility of doing whether the platform is 32/64 bit but does not give me enough freedom.
I would like to pass a variable to my makefile like
make includeMyLib=1
and depending on this having something like:
#ifndef includeMyLib
#include <myLib.h>
#endif
Do you know if anything like this is possible?
If you use GNU make, you could have something like this in the Makefile:
ifdef includeMyLib
CFLAGS += -DincludeMyLib
endif
This will change the flags used by the compiler to add the #define includeMyLib.

What are those gcc options doing?

In a makefile I work on, gcc is used with the -D XOPEN_SOURCE=500 and -D_BSD_SOURCE options. gcc --help does not tell me what these are; a quick google search didn't help either. I'm quite a newbie with gcc, could someone give me a hint?
According to the GCC documentation ("3.11 Options Controlling the Preprocessor"), the -D switch defines the macros XOPEN_SOURCE and _BSD_SOURCE with the values 500 and 1 respectively. It's as though you have this code at the beginning of all the source files you pass to GCC:
#define XOPEN_SOURCE 500
#define _BSD_SOURCE 1
Build scripts usually take advantage of the compiler's ability to "insert" macros like these to "communicate" to the source code details about the platform being targeted (e.g. operating system version).
The "opposite" command-line switch for -D is -U, which #undefs a macro.
Most (if not all) modern C/C++ compilers include similar switches. For example, Visual C++ compilers accept the /D compiler switch, which essentially serves the same purpose as GCC's -D switch.
For future reference, the GCC option index is great if you need to look up compiler switches for the GCC compiler.
-D is used to set defines. The source code you are compiling most likely is using those defines to include specific header files.
Think of -D as doing the same thing as:
#define XOPEN_SOURCE 500
#define _BSD_SOURCE 1
at the top of the file it is currently compiling.
These do not nothing for gcc. These are definitions like similar you have in your .c, .cpp or .h files:
#define XOPEN_SOURCE 500
#define _BSD_SOURCE
-D is equlivant of a #define
i.e.
#define XOPEN_SOURCE 500
-D sets a define. It's like adding a header file that contains:
#define XOPEN_SOURCE 500
#define _BSD_SOURCE 1
You can then use #ifdef _BSD_SOURCE to enable conditional compilation of certain part of the code.

Eclipse CDT syntax error on __attribute__ keyword

I would like to know if there is a way to get rid of CDT syntax error warnings when using gcc's "__attribute__" keyword.
It goes without saying that I would not like to switch off CDT syntax check.
The "ECLIPSE_THINKS_THIS_IS_SET_BUT_GCC_DOESNT" definition (from ams's answer) really extsts and it called __CDT_PARSER__. For example:
#ifdef __CDT_PARSER__
#define __FILE__ "<file>"
#define __LINE__ (-1)
#define __DATE__ "<date>"
#define __TIME__ "<time>"
#endif // #ifdef __CDT_PARSER__
Hope this will be helpful.
I've not tried it, and I've not used Eclipse for some time, but here's an idea:
In the CDT settings for Eclipse (or maybe just your project) set up a predefined macro (I seem to remember you can tell it what the compiler auto-defines) named __attribute__ that takes one parameter, and expands to nothing.
Maybe I haven't explained that right. Let me try again with an example. Basically, the aim is to define a macro that works like this:
#if ECLIPSE_THINKS_THIS_IS_SET_BUT_GCC_DOESNT
#define __attribute__(X) /* nothing */
#endif
but without putting anything actually in your code.
Project->Properties->C/C++ general->Path and Symbols->Symbols
Add->
Name: __attribute__(X)
Value: (leave blank)
Related links: You can use this technique basically with any offending keyword
ziu's answer is also working for XC8 Microchip compilers
Name: __interrupt
Value: (leave blank)
The function prototype now is clean:
void __interrupt ISRs(void);
And Eclipse won't complain about it.

How to undefine a define at commandline using gcc

How do I at compile time undefine a compiler macro using gcc. I tried some compile args to gcc like -D but I can't get to see the "not defined" message.
Thanks
#include <iostream>
#define MYDEF
int main(){
#ifdef MYDEF
std::cout<<"defined\n";
#else
std::cout<<"not defined\n";
#endif
}
You can use the -U option with gcc, but it won't undefine a macro defined in your source code. As far as I know, there's no way to do that.
You should wrap the MYDEF definition in a preprocessor macro, the presence of which (defined on the command line) would then prevent MYDEF from being defined. A bit convoluted to be sure but you can then control the build in the way you want from the command line (or Makefile). Example:
#ifndef DONT_DEFINE_MYDEF
#define MYDEF
#endif
Then from the command line when you don't want MYDEF:
gcc -DDONT_DEFINE_MYDEF ...
http://gcc.gnu.org/onlinedocs/gcc-4.4.2/gcc/Preprocessor-Options.html#Preprocessor-Options
The -U options seemed like what you could have needed... but then again you can't override a definition contained in your source code without resorting to more preprocessor directives.
You can resort to filtering source code and give this back to gcc for compilation, like this pseudo code:
grep -v "define MYDEF" yourFile.c | gcc -o yourFile.o -xc -
Hope it helps.
The code use case is not right. As I see, you have hard coded #define in the file. If compiler initially assumes MYDEF undefined, it will define it once it start processing the file.
You should remove the line #define MYDEF. And I hope your test case will work, if you pass MYDEF to -D and -U.
Here is one possibility that doesn't completely cover your use case but which I found to be helpful in my case.
If your MYDEF were #defined in a separate header file #included from the .c file you could force the definition of the #include guard macro with the -D option (thus preventing the MYDEF #definition) then either actively #define (still with the -D option) MYDEF to something else or just leave it undefined.
It is clear that anything else defined in the header file would also be missing but this was for me a solution to forcedly undefine a macro without changing the third-party code.

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