Let me start out with a disclaimer:
I am new to writing my own makefiles and have just had a few days of research and tinkering around with my own makefile to try to figure things out. I have also Googled this question and spent a fair amount of time looking for an answer but haven't found one. There are many things I am inexperienced with, so if I ask a stupid question, please bear with me (and try to help me understand it).
I have made a makefile that I have been testing out to see if my understanding is correct, and so far everything here makes sense and works until it gets to $(CC). I'm on windows 7 using cygwin64 terminal and it gives this output after I type make:
make: tricore-gcc: Command not found
make: *** [Makefile:20: test_eeprom.o] Error 127
So why can't it recognize my compiler? Why does it say "Command not found?" I know the compiler is installed because I have used it for existing projects on my computer and just now am starting to write my own makefile and try to use it. I have even seen in other makefiles that were made by someone previous to me that they define the compiler the same way as me in the makefile.
For reference, here is my makefile:
#Test module Makefile
#compiler
CC = tricore-gcc
#path to MBD header files
MBDPATH = ../../../../../../Application/MBD/build/test_ert_rtw
#where the source code is
SRC = Src
#object files to be made
DS_OBJ = test_eeprom.o test_gd.o test_task.o \
sct_conf.o unimportant_name.o
#rule to make test eeprom object
test_eeprom.o: $(SRC)/test_eeprom.c $(SRC)/test_eeprom.h $(SRC)/test_task.h \
$(MBDPATH)/test.h
$(CC) -c test_eeprom.
Related
This question already has an answer here:
make: Nothing to be done for `all'. when i tried to compile
(1 answer)
Closed 5 months ago.
Here is my snippet of code that's giving me this error, it is in Fortran. If you want more code I can amend this one if it helps.
[cba78749#bridges2-login012 ~]$ cd FFB0D
[cba78749#bridges2-login012 FFB0D]$ ls
BGKVDCF0D_commvar.f90 BGKVDCF0D_spat_oper_mod.o DGV_commvar.f90 DGV_miscsetup.o Makefile_debug bgkvdcf0d_spat_oper_mod.mod dgv_readwrite.mod gaussquad.mod nrroutines_mod.o
BGKVDCF0D_commvar.o BGKVDCF0D_time_integr_mod.f90 DGV_commvar.o DGV_mpiroutines.f90 Makefile_production bgkvdcf0d_time_integr_mod.mod dgv_sf02.mod gaussquad.o nrtype.f90
BGKVDCF0D_miscset.f90 BGKVDCF0D_time_integr_mod.o DGV_dgvtools_mod.f90 DGV_readwrite.f90 algama.f dgv_collision_mod.mod ffbM300.a makemake.perl nrtype.mod
BGKVDCF0D_miscset.o BGKVDCF0Driver.f90 DGV_dgvtools_mod.o DGV_readwrite.o algama.o dgv_commvar.mod gaussian_mod.f90 mkl_dft_type.mod nrtype.o
BGKVDCF0D_readwrite.f90 BGKVDCF0Driver.o DGV_distributions_mod.f90 DGV_sf02.f90 bgkvdcf0d_commvar.mod dgv_dgvtools_mod.mod gaussian_mod.mod mkl_dfti.mod nrutil.f90
BGKVDCF0D_readwrite.o DGV_collision_mod.f90 DGV_distributions_mod.o DGV_sf02.o bgkvdcf0d_miscset.mod dgv_distributions_mod.mod gaussian_mod.o nrroutines_mod.f90 nrutil.mod
BGKVDCF0D_spat_oper_mod.f90 DGV_collision_mod.o DGV_miscsetup.f90 Makefile bgkvdcf0d_readwrite.mod dgv_miscset.mod gaussquad.f90 nrroutines_mod.mod nrutil.o
[cba78749#bridges2-login012 FFB0D]$ make
make: Nothing to be done for 'all'.
I'm very new to PuTTY, and I'm trying to compile the code
It has nothing to do with putty. When you run make it looks for the Makefile (with exactly this capitalisation) and tries to make the first target it sees, in your Makefile that seems to be the target "all".
If the first target depends on other targets that haven't been met yet, it will also make those.
It is not uncommon to have the all target as the first target that simply depends on all the targets in the Makefile, that way running make will create all targets.
But if all targets are already made, meaning the files declared as target are newer than their own dependencies (sources), nothing needs to be made, and you get the message that you are inquiring about.
I strongly recommend reading up on the make command, for example here: https://linuxhint.com/gnu-make-tutorial/
I created a Makefile.in where I read the content out of a file and pass it to CFLAGS. Calling ./configure ... the Makefile will be generated an all works well.
Makefile.in:
...
MY_REVISION_FILE=my-revision.txt
MY_REVISION=$(shell cat $(top_srcdir)/$(MY_REVISION_FILE))
AM_CFLAGS = -I$(EXTRAS_INCLUDE_DIR) -I$(top_srcdir) -DMY_REVISION=$(MY_REVISION)
...
The problem arises once I moved the Makefile.in code into Makefile.am to allow the auto generation of Makefile.in. There calling autoreconf -i --force stops with the following error:
server/Makefile.am:9: cat $(top_srcdir: non-POSIX variable name
server/Makefile.am:9: (probably a GNU make extension)
autoreconf: automake failed with exit status: 1
This problem hunts me now since quite some time. I searched everywhere but did not find anything that could help me finding a solution for that. In short, the only thing I need is a way to get an uninterpreted text such as "$(shell cat $(top_srcdir)/$(MY_REVISION_FILE))" copied from Makefile.am to Makefile.in
Any idea?
Thanks,
Oliver
As it says, the problem is you're using a GNUism in your Makefile.am, when it's only meant to contain portable Makefile code.
Either rewrite your code so it's portable (you should use AM_CPPFLAGS because you're passing flags to the preprocessor, not the compiler):
AM_CPPFLAGS = -I$(EXTRAS_INCLUDE_DIR) -I$(top_srcdir) -DMY_REVISION=`cat $(top_srcdir)/$(MY_REVISION_FILE)`
If you don't want to invoke cat on every compile, you could find the value in configure.ac and either AC_SUBST it into Makefile or AC_DEFINE it so it goes into config.h.
Or if you want to be non-portable (ಠ_ಠ), you can take -Werror out of your AM_INIT_AUTOMAKE or AUTOMAKE_OPTIONS, or add -Wno-portability.
After long testing back and forth I decided to use AC_SUBST.
My solution might not be the cleanest but it works for me.
In configure.ac I added the following line
AC_SUBST([DOLLAR_SIGN],[$])
In the Makefile.am I changed my previous line into
MY_REVISION=#DOLLAR_SIGN#(shell cat $(SRC_DIR)/$(MY_REVISION_FILE))
And it works.
Again, thanks for your help.
I am trying to make a makefile for one cpp file. I've tried googling and none of the examples I've seen have helped... I keep getting errors when I type make. Here is what I have...
Interpreter: Interpreter.o
g++ -o Interpreter Interpreter.o
Interpreter.o: Interpreter.cpp
g++ -c Interpreter.cpp
When I type make I get this error... "'ake: Fatal error: Don't know how to make target `Interpreter.o"
Where am I going wrong?
OK. A few simple things to start with here:
As mentioned in some of the comments, the makefile file must be named properly for make to find it. You can try specifing it manually with the -f flag to verify that it is being found.
Make is one of those few unfortunate languages where whitespace is important. The rules must not have a tab in front of them, and the commands for the rules should all have exactly one tab in front of them. When I checked your code above in the SO editor, it looked like your commands had two tabs at the front instead of one.
If I'm reading those rules right, you need a file named Interpreter.cpp in your working directory for this to work. If you don't have that file, you'll get an error.
If all else fails, try running make with the debugging flag (-d). This should give you more information about the decisions it is making.
I'm trying to 'make' using a pretty simple makefile. My makefile is named 'Makefile' so I'm simply using the command 'make'.
I get this strange error:
make: *** No rule to make target `/Makefile', needed by `Makefile'. Stop.
If, however, I use
make -f "full-path-to-makefile" it actually does run (with odd consequences...). I should say that I'm running all this from the directory where the Makefile lies, of course.
I'm working on Mac OSX, using tcsh.
Edit:
I'm working in the LLVM framework, trying to compile a pass function and this is the associated makefile:
LEVEL = ../../../
LIBRARYNAME = FunctionName
LOADABLE_MODULE = 1
include $(LEVEL)/Makefile.common
Any ideas will be appreciated :)
I had the same problem trying to write a new pass for LLVM i followed these instructions trying to make a HelloB (as Hello already exsited) http://llvm.org/docs/WritingAnLLVMPass.html#quickstart
What i has to do was do a ./configure again then make from the base directory.
I'll go out on a limb: you have an extra slash. Try omitting the final slash in $(LEVEL).
I found the answer, sort of:
The problem was with the installation process of LLVM. It seems that if you do the installation in one order instead of another it can lead to this error. It doesn't make any sense to me, but after I installed it properly everything compiles great (same code, same Makefile, same make program).
I don't really know why this happened, but I know how to fix it :)
What you want to do is ./configure again then make from the base directory (contrary to what is stated in the instructions on the web-site). That worked for me.
BTW - I got the same results running on Ubuntu (with the same fix).
Just to add some information here (since this is the first hit that comes up on Google when looking for the error) - I had the same problem which suddenly popped up on a (previously working) LLVM setup on OSX, and traced it back to the behavior of the realpath command in make.
Specifically, what was happening was that I had a directory called "LLVM/llvm-2.9-build", but for some reason the attempt to resolve PROJECT_OBJ_ROOT at the top of Makefile.config would decide that this directory was in fact called "llvm/llvm-2.9-build". Since OSX is case-insensitive by default, this doesn't cause an immediate problem, except that subsequently LLVM_SRC_ROOT would be set to "LLVM/llvm-2.9-build". This then meant that the creation of PROJ_SRC_DIR using patsubst to replace the object directory would result in a non-existent path (as the unmatched case means that no pattern replace occurs), which in turn would get resolved to / by realpath.
With PROJ_SRC_DIR set to /, this results in the makefile copy rule in Makefile.rules deciding that the source makefile is at $(PROJ_SRC_DIR)/Makefile (ie /Makefile), and the error message described.
It seems that it is only the built-in implementation of realpath in Make (GNU Make 3.81 in my case) that has this behaviour, as forcibly using the macro version of realpath from the top of Makefile.config fixes the problem. However, this isn't a good long-term fix, as you'd have to manually patch every one of the LLVM makefiles.
In the end, I couldn't see where realpath would be getting the lower-case "llvm" from, but figured it was probably an artifact somehow of some caching of the name from a point in time when I'd referenced the directory using its lower-case name. Hence I tried going to that directory and mv-ing it to a completely different name, and then back to "LLVM" before going in and building again, and that seems to have solved the problem.
I hope that's of some use to anyone else who comes across this particular weirdness!
It's not a complete answer, but what you are seeing is gmake not finding the Makefile it is told to include, and thus it is trying to remake it and failing because it can't find a recipe for it either.
However, the Makefile snippet you posted does not produce the error message you are seeing, so I think the problem is inside the Makefile.common file. Look for include statements which reference a $(some variable expansion)/Makefile and work backwards from there. You can also try to run gmake with the -d option and follow the processing based on the output.
Since your include line reads:
include $(LEVEL)/Makefile.common
it is puzzling that you are not getting an error about /Makefile.common. If you were, then I'd suggest that maybe you have a trailing blank after the definition of LEVEL.
Could there be a line in Makefile.common that itself includes $(SOMEMACRO)/Makefile and you have not set the value of SOMEMACRO?
here's my fixes for this issue: (https://github.com/rust-lang/rust/issues/24887#issuecomment-99391849)
update src/llvm/Makefile.config.in before running ./configure
or update x86_64-apple-darwin/llvm/Makefile.config before make
line 59:
PROJ_SRC_DIR := $(LLVM_SRC_ROOT)$(patsubst $(PROJ_OBJ_ROOT)%,%,$(PROJ_OBJ_DIR))
update to
PROJ_SRC_DIR := $(patsubst $(PROJ_OBJ_ROOT)%,$(LLVM_SRC_ROOT)%,$(PROJ_OBJ_DIR))
line 86:
PROJ_SRC_DIR := $(call realpath, $(PROJ_SRC_ROOT)/$(patsubst $(PROJ_OBJ_ROOT)%,%,$(PROJ_OBJ_DIR)))
update to
PROJ_SRC_DIR := $(call realpath, $(patsubst $(PROJ_OBJ_ROOT)%,$(PROJ_SRC_ROOT)%,$(PROJ_OBJ_DIR)))
I am looking at C makefile, and I have a question.
I know that 'make a' will make the target a, which is supposed to be defined in the makefile.
I want to know whether the target name itself can be supplied as an argument to make.
i.e. this is what I want to do:
$(target_name) is the name supplied to command 'make'. For example, 'make foo'.
and in the makefile,
$(target_name) = dependencies
command
I am not sure whether this is possible... could not find anything in the make manual too.
If anyone can help me with this, it'll be awesome.
Thanks,
Everything you are asking about is what make does by default - there is no need to write any special code in the makefile to do this. You seem rather confused about make (it is not particularly C related, for example). The best guide to it is the GNU Make Manual, which is not only a manual but a pretty good tutorial.
I'm kind of new to Makefiles but it seems you don't pass values in Makefile like that. If the following is your Makefile
# Makefile
TARGET?=something
$(TARGET):
echo $(TARGET)
You can pass parameters in by calling make like this in the terminal
$ TARGET='ABCDEF' make