I have 2 wireless pci cards (same model, but can work under 2 different modes) on the bus. They share the same driver. What I want to do is to hack the driver like this: check the pci index, the first probed device (index 0) will be configured as mode A, the next one (index 1) will be configured as mode B.
so I want to know if they are probed in the same order every time the system init.
If the probe order is random, is there any other way can do that?
I tried this: plug the same card into difference slots, and check what I got under /sys/devices/pci0000:00. the result are all the same.
so the kernel know nothing about the physical slot at all? I was thinking maybe the kernel know which physical slot the card was mounted on. pity..
To answer: No, they are not in general.
To what you are trying to resolve: No need to do that since it's fixed in modern kernels Linux systems, The name of network interface is linked to the physical slot of the device. You will always have same names until you physically move the cards.
Correction. Initially I thought that this is provided by kernel. No, it's provided by user space helper, i.e. udev.
Names incorporating Firmware/BIOS provided index numbers for on-board devices (example: eno1)
Names incorporating Firmware/BIOS provided PCI Express hotplug slot index numbers (example: ens1)
Names incorporating physical/geographical location of the connector of the hardware (example: enp2s0)
Names incorporating the interfaces's MAC address (example: enx78e7d1ea46da)
Classic, unpredictable kernel-native ethX naming (example: eth0)
Origin: https://www.freedesktop.org/wiki/Software/systemd/PredictableNetworkInterfaceNames/
Example:
% ip link list dev enp0s20u2c2
42: enp0s20u2c2: <BROADCAST,MULTICAST,UP,LOWER_UP> mtu 1500 qdisc pfifo_fast state UP mode DEFAULT group default qlen 1000
link/ether 4a:06:8b:65:72:36 brd ff:ff:ff:ff:ff:ff
% ls -l /sys/class/net/enp0s20u2c2
lrwxrwxrwx 1 root root 0 Dec 23 14:59 /sys/class/net/enp0s20u2c2 -> ../../devices/pci0000:00/0000:00:14.0/usb1/1-2/1-2:2.0/net/enp0s20u2c2
Related
I'd like to find a way to figure out physical slot of a PCI-E device from the bus address. I would like to use to modify a driver/kernel module, so it would enumerate the devices (with the same ID) and disambiguate the device files according to physical slot. Like /dev/device_physslot . The driver will run on Ubuntu 18
lspci is capable to show physical slot number in the verbose presentation
However, as I found out, it accomplishes it over sysfs, which cannot be accessed from kernel module.
So I need to do it somehow with system calls.
Or perhaps it is possible to figure out, where sysfs gets /sys/bus/pci/slots/slot_num/address property?
First of all, I would say to you that I write this question from nothing because I have attempt to find good documentation but nothing stand out...
What happens when we squeeze a key?
I think this is complex but I hope you can help me.
What I search to know : all (but especially the program start on the host machine and how the key electric signal is encoded and send...)
The eXtensible Host Controller (xHC) has a Periodic Transfer Ring. Windows programs this ring to trigger a transfer every time an interval in milliseconds has passed. The right interval is specified in the USB descriptor returned by the USB device. When the transfer occurs, the xHC puts a Transfer Event TRB on the event ring and triggers an MSI-X interrupt which bypasses the IOAPIC as some kind of inter-processor interrupt. If Windows detects some change in the keys pressed, it will send a message to the application which currently has focus (calling the window's procedure) with the key pressed in one of the argument.
I don't know about electrical signals but I know the eXtensible Host Controller is the USB controller responsible to interact with USB on modern Windows systems. Since Windows nowadays requires an x64 processor, the xHC must be present on your motherboard. The xHC is a PCI-Express device which is compliant with the PCI-Express specification.
To find an xHC, you:
Find the RSDP ACPI table in RAM;
This table will be found by the UEFI firmware which acts as some kind of small operating-system (OS) during boot of the computer. Then, the OS developers will write a small UEFI application named bootx64.efi that they will place on a FAT32 partition on the hard-disk. They will place this app in the /boot/efi directory. The UEFI firmware will directly launch that application on boot of the computer which allows to have an OS which doesn't require user input to be launched (similarly to how it used to work with the legacy BIOS fetching the first sector of the hard-disk and executing the instructions found there).
The UEFI application is compiled in practice with either EDK2 or gnu-efi. These compilers are aware of the UEFI environment and specification. They thus compile the code to system calls that are present during boot and available for the UEFI application written by the OS developers. The System Tables (often the ACPI tables) are given as an argument to the "main" function (often called UefiMain) called by the UEFI firmware in the UEFI application. The code of the application can thus simply use these arguments to find the RSDP table and pass it to the OS.
Find the MCFG ACPI table using the RSDP;
The chain of table is RSDP -> XSDT -> MCFG. Once the OS found the MCFG, this table specifies the base address of the PCI configuration space. To interact with PCI devices you use memory mapped IO (MMIO). You write to some position in RAM and it will instead write to the registers of the PCI devices. The MCFG thus specifies the base address at which you will start finding MMIO registers for the different PCI devices that are plugged into the computer.
Iterate on the PCI devices and look at their IDs until you find an xHC.
To iterate on the PCI devices, the PCI convention specifies a formula which is the following:
UINT64 physical_address = base_address + ((bus - first_bus) << 20 | device << 15 | function << 12);
The base_address is for a specific segment group. Each segment group can have 256 buses (suitable for large servers or large computers with lots of components). There can be up to 65536 segment groups and each can have up to 256 PCI buses. Each PCI bus can have up to 32 devices plugged onto it and each device can have up to 8 functions. Each function can also be a PCI bridge. This is quite straightforward to understand because the terminology is clear. The bus here is an actual serial bus that the PCI devices (like a network card, a graphics card, an xHC, an AHCI, etc.) use to communicate with RAM. The function is a functionality of the PCI device like controlling USB devices, hard-disks, HDMI screens (for graphics cards), etc. The PCI bridge bridges a PCI bus to another PCI bus. It means you can have almost an infinite amount of devices with the PCI specification because the bridges allow to extend the tree of devices by adding other PCI host controllers.
Meanwhile, the bus is simply a number between 0 and 255. The first bus is specified in the MCFG ACPI table for a specific segment group. The device is a number between 0 and 31 and the function is a number between 0 and 7. This formula returns a physical address which points to a conventional configuration space (it is the same for all functions) which has specific registers. These registers are used to determine what is the type of device and to load a proper driver for it. Each function of each device thus gets a configuration space.
For the xHC, there will be only one function and the IDs returned by its configuration space will be 0x0C for the class ID and 0x03 for the subclass ID (https://wiki.osdev.org/EXtensible_Host_Controller_Interface).
Once you found an xHC, it gets rather complex. You need to initialize it and get the USB devices which are plugged in the computer at the current moment. You need to take several steps to get the xHC operational. For this part, I'll leave you to read the xHCI specification which (on chapter 4) specifies exactly the steps which need to be taken (https://www.intel.com/content/dam/www/public/us/en/documents/technical-specifications/extensible-host-controler-interface-usb-xhci.pdf).
For the keyboard portion I'll leave you to read one of my answer on the stackexchange for computer science: https://cs.stackexchange.com/questions/141870/when-are-a-controllers-registers-loaded-and-ready-to-inform-an-i-o-operation/141918#141918.
Some good links:
https://wiki.osdev.org/Universal_Serial_Bus
https://wiki.osdev.org/PCI
I have a custom linux kernel driver that communicates to an old ISA card (from an old single processor pc with a true ISA bus). I am trying to port this driver into a new system equipped with a PCI-ISA bridge.
The old driver was writing to I/O ISA ports with:
request_region(0x0280, 8, "foo"); //0x0280 is a jumper-configured address in ISA card hardware.
//Then lots of:
outw_p(val, 0x0280);
val = inw_p(0x0282);
... (ports in use 0x0280, 0x0282 and 0x0284)
I've tried the same code but the address mapping seems to not work anymore. Region request does not give errors, but I keep getting always 65535 from all inw_p reads (while in the old system with the same code the card was answering with meaningful data).
I can't find anywhere what to edit in this code to make it work with the bridge.
I've tried opening the bridge as a PCI device and getting its I/O port address with:
dev = pci_get_device(vid, id, NULL); //Called with hardcoded bridge ids from lspci
result = pci_enable_device(dev); //dev not null, no errors
result = pci_request_regions(dev, "foo"); //No errors
value = pci_resource_start(dev, bar); //value is always 0 with any bar value
Device is working as I can get its vendor id by using pci_read_config_word, but I get always 0 from any BAR value, and also lspci -vvvv gives me no address/region section:
04:08.0 ISA bridge: Integrated Technology Express, Inc. IT8888F/G PCI to ISA Bridge with SMB [Golden Gate] (rev 03)
Control: I/O+ Mem+ BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B- DisINTx-
Status: Cap- 66MHz- UDF- FastB2B+ ParErr- DEVSEL=medium >TAbort- <TAbort- <MAbort- >SERR- <PERR- INTx-
Latency: 0
Also, no configuration options seems to be available in BIOS for this bridge.
On the internet i found only a few infos about PCI - ISA bridges in general, so I'm asking: what is the procedure necessary to successfully communicate with an ISA card behind a PCI - ISA bridge from a custom linux kernel driver?
Ok, after a lot of trial and error I was able to find the problem. I will share my experience in hope for someone to find it useful (my pc has a HD620-H81 motherboard with IT8888F/G PCI-ISA bridge).
PCI-ISA bridge
My PCI-ISA bridge (and probably many others) is configured by default in "Subtractive Decoding" pci mode, which means "if no other pci device claim an address, then the bridge claims it".
You can check for subtractive decoding mode by running lspci -t and lscpi -vv, and you should see that every PCIe-PCI/PCI-PCI bridge in the tree leading to your PCI-ISA bridge is configured in subtractive decode mode (the ISA bridge itself won't appear as subtractive because from a PCI perspective the ISA bridge is just a PCI device and not a bridge).
That means that you don't have a BAR assigned to the bridge, nor you need to interact with the pci bridge device directly in any way. You can just access directly the absolute address you need and the bridge will take care of managing it correctly (a lot of information is already available on the internet for subtractive decoding anyway if you're interested in details).
To sum up: no action is needed regarding the bridge itself or pci devices, just make sure in the bios that no other device, such as serial or parallel ports, gets assigned the port/address range that you are interested into (if it does, either disable it or change its address).
I/O Ports
I found that my ISA card was located at a port which is 0x0800 ports above the one where it should be (and that was the main problem for me). I'm not sure about why, maybe my bridge adds a fixed offset (if you know the reason maybe comment it below!).
What I did to find out the correct address was to run a function that iterates all port addresses from 0x0100 (which skips the first zone where is better not to write random data into) to 0xFFFF and runs a card check routine at each single port address until it finds the correct answer I expected from the card.
int cardFound = 0;
int i;
for(i = 0x0100; i < 0xFFFF && !cardFound; i++)
{
if (request_region(i, SIZE) == NULL)
continue;
//Do card detection with ioport_map, iowrite16/ioread16, etc.
cardFound = do_custom_card_detection_procedure();
release_region(i, SIZE);
}
if (cardFound)
printk(KERN_INFO "Card found at port %d\n", i);
The downside of this approach is that you may do really bad things by randomly writing data at ports, so be careful and if you really want to try check /proc/ioport for bad ones before doing it (I messed up rendering for a quarter of the screen and I had to do a complete power reset by removing power cord and CMOS battery to bring it back to normal :D).
How does Linux Kernel or BIOS map the PCIe endpoint device memory into systems MMIO space ? Is there any API to achieve it ?
Lets assume that when writing a Linux device driver for a PCIe endpoint device, How can we map PCIe device memory into MMIO space ? Or Is it true that the device is already mapped into MMIO by BIOS during enumeration and what I would need to do it just remap the device MMIO into the kernel virtual address space using ioremap() ?
Platform : Linux on x86
There are two parts to this answer
Role of the BIOS
The BIOS (typically UEFI based) will do some sort of Depth-First Search (DFS) and enumerate all the children as PCIe is a self-enumerating bus. Since it has the view of the world (device, buses, processors) it will write an address to the BAR registers (could be BAR0 and or multiple of them). This will be the address the system will use and it will actually route these requests from the Host Agent (HA on x86/Intel platforms) to the Root Port to a PCIe switch all the way to the end point.
Each of these elements track what address ranges belong to themselves or one of their child devices (example a Switch may be the child of a Root Port)
Role of the Device Driver
The OS/Kernel will provide a toolkit of helper routines that the driver authors will use to access the device registers. Typically a driver may follow the folling routines
This is some sample driver pseudo-code, just to help illustrate the idea
1. pci_resource_flags(pdev, 0) & IORESOURCE_MEM
Check if a resource region is valid, here check for BAR 0
2. pci_request_regions(pdev, "region")
Take ownership of the resource/region
3. drv->registers = pci_iomap(pdev, 0, SIZE_YOU_WANT_TO_MAP)
This will give you kernel virtual address to device register mapping
Note : In case the BIOS does not enumerate, through Linux one can rescan the PCIe tree to see if a device can be seen or not.
I have an FPGA (Like most of the people asking this question) that gets configured after my Linux kernel does the initial PCIe bus scan and enumeration. As you can guess, the FPGA implements a PCIe endpoint.
I would Like to have the PCIe core re-enumerate the ENTIRE PCIe bus so that my FPGA will then show up and I can load my driver module. I would also like the ability to SWAP the FPGA load out for a different configuration. By this I mean I would like to be able to:
Boot Linux
Configure FPGA
Enumerate PCIe endpoint and load module
Remove PCIe endpoint
Re-configure FPGA
Re-enumerate PCIe endpoint
All without rebooting Linux
Here are solutions that have been proposed elsewhere but do not solve the problem.
echo 1 > /sys/bus/pci/rescan This seems to work (only sometimes) and it does not work if I want to hotswap the FPGA load after it was first enumerated.
Can the Hotplug/power managment facilities of PCIe be used to make this work? If so is there any good resources for how to use the Hotplug system with PCIe? (LDD does not quite cover it thoroughly enough)
Re-enumerating the PCIe bus/tree via echo 1 > /sys/bus/pci/rescan is the correct solution. We are using it the same way as you described it.
We are using echo 1 > $pcidevice/remove to disconnect the driver from the device and to detach the device from the tree. The driver (xillybus) is not unloaded, just disconnected.
A better solution is to rescan only the node where your FPGA is attached to. This reduces the over all impact for the system.
This technique is used in the RC3E FPGA cloud system.
This is really dependent on exactly what is changed on the FPGA. The problem is in how PCIe enumeration and address assignment is done, particularly how the PCIe switches are configured. The allocation MUST be done in one shot as a depth-first search. After this is complete, it is not possible to go insert additional bus numbers or address space without changing all of the subsequent allocations, which would require reloading all of the corresponding device drivers. Basically, once the bus is enumerated and addresses are assigned, you can't change the overall allocations without re-enumerating the entire bus, which requires a reboot. Preallocating resources on a specific PCIe port can alleviate this problem, and is required for PCIe hot plugging.
If the PCIe BAR configuration has not changed, then usually doing a remove/hot reset/rescan is sufficient and no reboots are required.
If the BAR configuration has changed, then it's a different story. If the new BARs are smaller, then there should be no problem. But if the new BARs are larger or there are more BARs, if there isn't enough address space allocated to the switch port that the device is attached to, then those BARs cannot be allocated address space and the device will fail to enumerate. In this case, a reboot is required to so that resources can be reassigned. Don't forget that there are also 32 bit BARs and 64 bit BARs and these BARs are assigned form two different pools of address space, so changing BAR types can also require a reboot to re-enumerate.
If you're going from no device to a device (i.e. blank FPGA to configured FPGA), then bus numbers may need to be reassigned, which requires a reboot.
From The Doctor
Here is how to reset the Vegas before same as a reset in windows. This is based on the Vendor ID.
lspci -n | grep 1002: | egrep -v ".1"| awk '{print "find /sys | grep ""$1"/rescan" -| tac -;"}' | sh - | sed s/^/echo\ 1\ >\ "&/g | sed s/$/"/g
The output of that put in your /etc/rc.local to reset your Vegas after bootup similar to the devcon restart script.
echo 1 > "/sys/devices/pci0000:00/0000:00:01.0/0000:01:00.0/rescan"
echo 1 > "/sys/devices/pci0000:00/0000:00:1c.5/0000:03:00.0/rescan"
echo 1 > "/sys/devices/pci0000:00/0000:00:1d.0/0000:06:00.0/rescan"
echo 1 > "/sys/devices/pci0000:00/0000:00:1d.1/0000:07:00.0/rescan"